International Journal of Reconfigurable Computing: Vol 2012, No 1

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International Journal of Reconfigurable Computing

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Open SystemC Simulator with Support for Power Gating Design

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures

Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic

A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme

HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs

A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication

Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation

Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig′10)

Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders

Modeling and Implementation of a Power Estimation Methodology for SystemC

An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H

Cellular Automata-Based Parallel Random Number Generators Using FPGAs

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems

HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture

QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection

A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos

An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots

High-Performance Reconfigurable Computing

Evaluation of Runtime Task Mapping Using the rSesame Framework

A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers

High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP

An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response

A Protein Sequence Analysis Hardware Accelerator Based on Divergences

Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA

Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography

The “Chimera”: An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform

Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application

A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision

Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices

Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures

Occam-pi for Programming of Massively Parallel Reconfigurable Architectures

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

Exploring Many-Core Design Templates for FPGAs and ASICs

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