The relationship between the Q factor and the phase margin of the GHz-bandwidth super-source-follower-based low-pass filters is revealed. A 4th-order low-pass filter is then implemented using 90-nm CMOS technology, and the filter delivers a bandwidth of 1.3 GHz, P_1dB of −11.94 dBm, and IIP₃ of −4.5 dBm.

This paper presents a comprehensive study of Class-E/F₂ and inverse Class-F Power Amplifiers (PAs) designed for 35-42 GHz millimeter-wave applications, utilizing a 130 nm CMOS process with a comprehensive study and analysis of the limiting factors in the amplifier efficiency. The first proposed power amplifier is based on the class-E/F₂ architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network while the second suggested power amplifier is constructed using the inverse class-F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed class-E/F₂ and inverse class-F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency.

A new type of class E multiplier, that is, voltage-source parallel resonant class E multiplier, is proposed and designed. And the detailed analysis process is given. This new type of multiplier can operate with soft-switching conditions without DC-feed inductance or DC block capacitance. Two resonant filters are applied to decrease the harmonic components in the output voltage. The transistor voltage stress and circuit volume decreased greatly. The output power is much greater than in previous work. The voltage-source parallel resonant class E multiplier is more suitable for applications.

The pseudo-Doherty load-modulation balanced power amplifier (LMBA) consists of an asymmetric LMBA configuration and an asymmetrical coupler, thus greatly expanding the OBO. An LMBA with an OBO of 15 dB operating across 3.4–3.6 GHz is realized. The LMBA implemented here shows state-of-the-art performance in terms of the OBO range.

The co-design of power amplifiers (PA) and filter. PAs are often followed by filters to provide the out-of-band rejection and thus improve the signal-to-noise ratio. However, due to the limitation on the antenna element spacing, this configuration is too large in system and the interconnections have a high insertion loss. So, integrating the functionality of filtering response into the PAs is a more compact and lower loss scheme.

• This paper evaluates popular methods for balancing CR-VCOs' outputs.
• It assesses the effectiveness of those methods in terms of mismatch cancellation, PVT robustness, and phase noise.
• This work proposes a CR-VCO with inherent ability to generate balanced outputs. It is achieved by implementing single-ended tank capacitors to shunt the common-mode voltage to a real ground.

An instrumentation amplifier aimed at wideband bioimpedance analysis in the low-voltage low-power scenario of internet of medical things and supplied with 0.6 V is presented. Experimental results in 180 nm CMOS technology are provided.

Hall sensors produce an output after every sixty degrees of rotation of the rotor, generating six sequences (called sector here) in one electrical cycle. Based on this sector information in each electrical cycle, a simple detection strategy for the Hall sensor fault is proposed. A pseudo-Hall sensor signal is generated from the healthy Hall sensor signal to reconstruct the faulty signal/s.

This paper presents an innovative study on theoretical design and test methodology of circuit exhibiting positive to negative tunable delay by using unfamiliar NGD topology.

This article proposes to transfer maximum power from a power supply to an induction heating load by matching the dynamic resistance of the induction heating resonant circuit with the internal resistance of the power supply source, as shown in Figure (A). The proposed method includes selecting a capacitor C_P, as shown in Figure (B), connected in parallel to the induction coil and tuning the correct value of the inverter frequency to the induction heating circuit resonant frequency. At resonance (Figure C), maximum power is transferred when the dynamic resistance of the resonant circuit is equal to the internal resistance of the DC power supply.

This paper proposes a novel behavioral model of GDDSCR device, which enables simulation of the bidirectional discharge path and snapback characteristics of ESD devices. The model parameters can be directly extracted from TLP tests, making it easy to apply to DDSCR devices. Experimental results demonstrate that the behavior model accurately reproduces the quasi-static IV characteristics with a good fit to the measured TLP IV characteristics.

To reduce the SHC, this paper proposes a strategy of virtual LC series resonant circuit with notch filter (NF-VLCSRC). Compared with publicly available literature, this paper uses the principle of LC series resonant circuit to reduce SHC and analyzes the mechanism of reducing SHC from the perspective of output impedance.

In this paper, a new group of active impedance source inverters, along with a suitable control method based on the pulse width modulation (PWM) technique, is presented. Using the proposed control method to produce the gate pulse of the switches, all operating modes of one of the proposed inverters, in two different operations (synchrony and asynchrony), to calculate boost factor and critical inductance in the boundary condition, are analyzed. The comparative analysis from different points of view, such as boost factor, total voltage blocked by diodes and switches, and voltage stresses on capacitors between the proposed topology and conventional structures to examine the advantages and disadvantages, is done.

During iterations, as the efficiency constraint increases, the efficiency constraint of the previous iteration is the maximum efficiency that the converter can achieve when no results exist. Meanwhile, the current change rate and the corresponding driving parameters can be obtained. Based on the slope of the current change rate and the efficiency, the Pareto solution can be divided into three areas. Among them, Areas 2 and 3 have a more obvious efficiency improvement than Area 1, but Area 3 also brings a higher current change rate lift after passing through Area 2. Therefore, the intersection of Areas 1 and 2 is the best compromise point for efficiency and electrical stress.

This paper proposes a zero-input-current-ripple (ZICR) high-voltage-gain dc-dc converter with an integrated Y-source network. It achieves zero input current ripple by introducing a parallel branch of an extra inductor, a coupled winding, and a capacitor at the input port. The voltage of the added inductor is opposite to that of the coupled winding. By adding the Y-source coupled inductor, the boost capability of the converter is improved. The unique boost circuit structure makes that one winding in the three-winding coupling inductance is step-down type (the turns ratio n₂ < 1) while the other winding is step-up type (the turns ratio n₁ > 1). In such a case, high voltage gain can be obtained under a lower turn ratio of the coupled inductor. The inherent passive clamping circuit clamps the spike voltage noises of the main switch to a low level and improves the efficiency. All the diodes have achieved ZCS (zero current switching) turn-off. By comparing with several new converters, the advantages of this converter are proved. Finally, a 200-W, 48- to 380-V, 50-kHz experimental prototype is built based on the theoretical research. At the rated power, the measured efficiencies with and without ZICR are 95.2% and 95.6%, respectively.

This paper presents a commutation torque ripple suppression method based on the minimum phase shift angle (MPSA) of hall signals. It is implemented through shifting hall signals by the MPSA and the MPSA is derived based on the unit duty cycle of the incoming and non-commutation phase. With the proposed method, the reliability is enhanced and no hardware is required, which reduces design cost and volume size. Finally, the proposed method is verified through simulation and experimental results.

We derived the formula for calculating the mutual inductance value of a circular coil with a double-layer metal shielding material and designed a fast calculation and adjustment strategy for the mutual inductance value of the coil using an intelligent optimization algorithm.

This research suggests to enhance the performance of electric vehicles (EVs) by integrating the proposed Ultra-Extended Boost Active Switch Controlled Quasi Z-source Inverter (UEBASC-qZSI) to power a BLDC motor. The implementation of a modified direct torque control method alongside UEBASC-qZSI aims to minimize torque distortion, resulting in improved EV efficiency and enhanced overall driving cycle safety. To verify the system's effectiveness, a Simulink model is developed in the MATLAB platform and is experimentally validated through a hardware prototype model.

This paper introduces a single-phase five-level inverter design using one DC source and a capacitor that possesses self-voltage balancing capability. The gate pulses are generated by using both SPWM and SVPWM techniques. Experimental setups and real-time implementation confirmed the viability of the proposed topology highlighting various applications.

The article's approach to circuit and system simulation is illustrated in the graphical image. Circuit simulations of NMC and DACFC amplifiers are discussed using HSPICE. The approximate transfer functions (TFs) are calculated by mapping the amplifiers to the graph domain to compare the accuracy between circuit and system simulation results.

The three-phase common-ground-type transformerless dual-buck inverters (DBIs) are derived. By shorting the neutral point of the three-phase load and the negative terminal of the PV panel, the common mode leakage current (CMLC) is eliminated. The DBIs have no shoot-through problem, and there is no current flowing through the body diode of the SiC MOSFET.

This work emphasizes the critical role of a well-designed high-efficiency DC-DC converter in the context of proton exchange membrane fuel cell (PEMFC) electric vehicle battery charging system. The proposed converter's innovative design, minimal componentry, efficiency, and validated performance through simulation, experimentation, and theory underscore its potential significance in enhancing PEMFC vehicle technology.

The proposed 13-level reduced multilevel inverter prioritizes optimized switch count for increased efficiency, utilizing Nearest Level Control (NLC) modulation for precise waveform control. This innovative design delivers cost-effectiveness without compromising performance, offering a compelling alternative to traditional multilevel inverters.

The implementation of a harmonic suppression strategy for VSG based on an enhanced linear extended state observer and PR-LADRC. The objective is to augment power quality by effectively mitigating harmonic disturbances in the system.

The paper presents an innovative stacked bidirectional nonisolated DC-DC converter designed for UPS applications. This advanced system boasts efficiency, simplicity, and a minimized component count. Model validation and comparative evaluations underscore its superior performance. A 1 kW prototype validates practical viability, achieving an impressive 96.38% efficiency in step-up and 95.7% in step-down modes.

This paper proposes an integrated modular equalization circuit for energy storage systems. This integration is achieved by reusing the half-bridge circuit into the cell-level equalization circuit and the module-level equalization circuit, thereby simplifying the system and saving costs.

In order to reduce the influence of double-node upset (DNU) on latches in single-event effects (SEE) and solve the problem of high power of the other latches, a new radiation hardened by design (RHBD), namely low-power double-node-upsets hardened latch (LPDHL) based on dual-interlocked storage cell (DICE) is proposed.

In this paper, we construct molecular switch circuits (MSCs) using DNA strand displacement. These circuits enable the realization of functions such as AND, OR, Fan-in, and Fan-out by cascading switches in series or parallel configurations. Additionally, we demonstrate the feasibility of these circuits by constructing a half-adder, half-subtractor, and a 9-bit parity checking circuit.

This paper presents designs of 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder based on novel designs of standard ternary inverter, ternary NAND, and ternary NOR logic gates using RRAM and CNTFET technology. Results indicate an improvement in power consumption, delay, power–delay product, and component count in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of PVT variations on the performance metrics of the proposed designs.

This graphical image describes an oscillator built around four impedances and two gain stages. The impedances can be separate R and C impedances or series and parallel RC combintaions. The gain stages can be opamp-based inverting and noninverting amplifiers or use any other active device. High- and low-frequency oscillators can be constructed based on this topology.