ORIGINAL ARTICLE
Utilizing signal flow graph on multiple feedback amplifiers of NMC and DACFC with emphasis on design space exploration and conversion
Masume Ghashghai,
Mohammad Bagher Ghaznavi-Ghoushchi,
Masume Ghashghai
Department of Electrical Engineering, Shahed University, Tehran, Iran
Search for more papers by this authorCorresponding Author
Mohammad Bagher Ghaznavi-Ghoushchi
Department of Electrical Engineering, Shahed University, Tehran, Iran
Correspondence
Mohammad Bagher Ghaznavi-Ghoushchi, Department of Electrical Engineering, Shahed University, Tehran, Iran.
Email: [email protected]
Search for more papers by this authorMasume Ghashghai,
Mohammad Bagher Ghaznavi-Ghoushchi,
Masume Ghashghai
Department of Electrical Engineering, Shahed University, Tehran, Iran
Search for more papers by this authorCorresponding Author
Mohammad Bagher Ghaznavi-Ghoushchi
Department of Electrical Engineering, Shahed University, Tehran, Iran
Correspondence
Mohammad Bagher Ghaznavi-Ghoushchi, Department of Electrical Engineering, Shahed University, Tehran, Iran.
Email: [email protected]
Search for more papers by this authorSummary
Over a long time, different methods of frequency compensation of multistage amplifiers have been exploited for improvement in the behavior of stabilizing. In the present paper, the step-by-step conversion process of the dual active capacitive feedback compensation (DACFC) three-stage amplifier into the nested Miller compensation (NMC) three-stage amplifier is presented by a systematic approach and signal flow graphs (SFGs) based on the graph theory rules in graph domain. Also, according to graph rules, the conversion of the multiple feedback amplifier NMC into the multiple feedback amplifier DACFC is investigated in detail in the graph domain. During the conversion process, the difference in the gain-bandwidth product (GBW) in the two mentioned case study's amplifiers is examined in terms of the graph at the system level. The elimination of two branches in one step of the conversion process of the SFG of the NMC into the SFG of the DACFC leads to a significant improvement in the behavior of GBW. This paper also conducts verification of the design of conventional NMC and DACFC amplifier circuits in HSPICE using 0.35-μm CMOS technology and compares the circuit simulation results to SFG simulation results. In order to show the correctness of the idea, they are redesigned in HSPICE using 0.18-μm CMOS technology, and appropriate results are obtained.
Open Research
DATA AVAILABILITY STATEMENT
The datasets generated and/or analyzed during the current paper are available from the corresponding author upon reasonable request.
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