VLSI Design: Vol 15, No 3

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Open Access

Timing-Driven-Testable Convergent Tree Adders

Article

Open Access

CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization

Article

Open Access

Improving the Timing of Extended Finite State Machines Via Catalyst

Article

Open Access

Performance Driven Global Routing Through Gradual Refinement

Article

Open Access

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

Article

Open Access

Energy Efficient Signaling in Deep-submicron Technology

Article

Open Access

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation

Article

Open Access

Timing Analysis and Optimization for DSM IC—Guest Editorial

Article

Open Access

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

Article

Open Access

A New Characterization Method for Delay and Power Dissipation of Standard Library Cells

Article

Open Access

Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis

VLSI Design

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Timing-Driven-Testable Convergent Tree Adders

CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization

Improving the Timing of Extended Finite State Machines Via Catalyst

Performance Driven Global Routing Through Gradual Refinement

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

Energy Efficient Signaling in Deep-submicron Technology

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation

Timing Analysis and Optimization for DSM IC—Guest Editorial

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

A New Characterization Method for Delay and Power Dissipation of Standard Library Cells

Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis

VLSI Design

Journal list menu

Tools

Follow journal

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Timing-Driven-Testable Convergent Tree Adders

CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization

Improving the Timing of Extended Finite State Machines Via Catalyst

Performance Driven Global Routing Through Gradual Refinement

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

Energy Efficient Signaling in Deep-submicron Technology

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation

Timing Analysis and Optimization for DSM IC—Guest Editorial

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

A New Characterization Method for Delay and Power Dissipation of Standard Library Cells

Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis