Article Index - International Journal of Reconfigurable Computing

All International Journal of Reconfigurable Computing Articles

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Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip
William V. Kritikos, Andrew G. Schmidt, Ron Sass, Erik K. Anderson, Matthew French,

First published: 26 January 2012

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Research Article
Open Access

oa

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors
Mariusz Grad, Christian Plessl,

First published: 11 January 2012

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Research Article
Open Access

oa

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks
Angelo Kuti Lusala, Jean-Didier Legat,

First published: 04 January 2012

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Research Article
Open Access

oa

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation
Indranil Hatai, Indrajit Chakrabarti,

First published: 25 December 2011
Research Article
Open Access

oa

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform
Joshua S. Monson, Mike Wirthlin, Brad Hutchings,

First published: 01 December 2011

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Research Article
Open Access

oa

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution
Kaveh Aasaraai, Andreas Moshovos,

First published: 29 November 2011

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Research Article
Open Access

oa

Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment
Tom Davidson, Fatma Abouelella, Karel Bruneel, Dirk Stroobandt,

First published: 17 November 2011

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Research Article
Open Access

oa

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection
Sascha Mühlbach, Andreas Koch,

First published: 09 November 2011

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Research Article
Open Access

oa

PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability
O. Ahmed, S. Areibi, K. Chattha, B. Kelly,

First published: 01 November 2011
Research Article
Open Access

oa

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms
Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow,

First published: 31 October 2011

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Research Article
Open Access

oa

Exploring Many-Core Design Templates for FPGAs and ASICs
Ilia Lebedev, Christopher Fletcher, Shaoyi Cheng, James Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek,

First published: 17 October 2011

Collections: Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Editorial
Open Access

oa

Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC’ 2010)
Michael Hübner, Jürgen Becker, Loïc Lagadec, Gilles Sassatelli,

First published: 12 October 2011

Collections: Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010)
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Research Article
Open Access

oa

Reduced-Precision Redundancy on FPGAs
Brian Pratt, Megan Fuller, Michael Wirthlin,

First published: 12 October 2011
Research Article
Open Access

oa

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC
Dominique Blouin, Daniel Chillet, Eric Senn, Sébastien Bilavarn, Robin Bonamy, Christian Samoyeau,

First published: 11 September 2011
Research Article
Open Access

oa

Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption
R. Al-Haddad, R. Oreifej, R. A. Ashraf, R. F. DeMara,

First published: 25 August 2011
Research Article
Open Access

oa

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback
John C. Hoffman, Marios S. Pattichis,

First published: 17 August 2011
Editorial
Open Access

oa

Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)
Aravind Dasu, João M. P. Cardoso, Eli Bozorgzadeh, Jürgen Becker,

First published: 30 June 2011

Collections: Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)
- Full text
- PDF
Research Article
Open Access

oa

A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture
Mohsin Amin, Abbas Ramazani, Fabrice Monteiro, Camille Diou, Abbas Dandache,

First published: 28 June 2011

Collections: Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010)
Research Article
Open Access

oa

Exploring Online Synthesis for CGRAs with Specialized Operator Sets
Stefan Döbrich, Christian Hochberger,

First published: 22 June 2011

Collections: Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010)
Research Article
Open Access

oa

A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips
Onur Derin, Erkan Diken, Leandro Fiorin,

First published: 19 June 2011

Collections: Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010)

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International Journal of Reconfigurable Computing

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All International Journal of Reconfigurable Computing Articles

oa

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

oa

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

oa

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

oa

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

oa

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

oa

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

oa

Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment

oa

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

oa

PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

oa

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

oa

Exploring Many-Core Design Templates for FPGAs and ASICs

oa

Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC’ 2010)

oa

Reduced-Precision Redundancy on FPGAs

oa

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

oa

Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

oa

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

oa

Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)

oa

A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

oa

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

oa

A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

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All International Journal of Reconfigurable Computing Articles

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oa Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

oa On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

oa Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

oa A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

oa A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

oa NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

oa Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment

oa A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

oa PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

oa Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

oa Exploring Many-Core Design Templates for FPGAs and ASICs

oa Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC’ 2010)

oa Reduced-Precision Redundancy on FPGAs

oa AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

oa Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

oa A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

oa Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)

oa A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

oa Exploring Online Synthesis for CGRAs with Specialized Operator Sets

oa A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

oa

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

oa

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

oa

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

oa

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

oa

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

oa

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

oa

Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment

oa

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

oa

PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

oa

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

oa

Exploring Many-Core Design Templates for FPGAs and ASICs

oa

Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC’ 2010)

oa

Reduced-Precision Redundancy on FPGAs

oa

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

oa

Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

oa

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

oa

Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)

oa

A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

oa

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

oa

A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips