Passives Technology
Professor Lih-Tyng Hwang
Department of Electrical Engineering and Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Search for more papers by this authorProfessor Tzyy-Sheng Jason Horng
Department of Electrical Engineering and Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Search for more papers by this authorProfessor Lih-Tyng Hwang
Department of Electrical Engineering and Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Search for more papers by this authorProfessor Tzyy-Sheng Jason Horng
Department of Electrical Engineering and Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Search for more papers by this authorSummary
This chapter is about the technologies for the passives, those on-chip, embedded (EPs), and integrated passive devices (IPDs). It discusses the SMA assembly processes that include the solder masks, underfill, and reflow. The chapter also discusses the fabrication technologies for on-chip, embedded, and IPDs. The chapter introduces different types of passives: homogeneous on-chip and heterogeneous off chip. It presents the design considerations specific to passives, including parasitic-scaling effects, the proximity requirement, and RF isolation techniques. Passives design becomes interesting because of these two opposing design requirements. The chapter also describes the technologies for these passives, including back end of the line (BEOL)/front end of line (FEOL), thick-film ceramic (TFC), laminate organic (LO), and thin-film multilayer (TFM). It also describes the multilayer organic (MLO) for, integrated circuit (IC) and passives. Multi-layer ceramic (MLC), MLO, FEOL, BEOL, and TFM are technology solutions for RF CMOS and RF-passives systems.
References
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- Ibid.
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