Chapter 2
Interconnects
Professor Lih-Tyng Hwang,
Professor Tzyy-Sheng Jason Horng,
Professor Lih-Tyng Hwang
Department of Electrical Engineering and Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Search for more papers by this authorProfessor Tzyy-Sheng Jason Horng
Department of Electrical Engineering and Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Search for more papers by this authorBook Author(s):Professor Lih-Tyng Hwang,
Professor Tzyy-Sheng Jason Horng,
Professor Lih-Tyng Hwang
Department of Electrical Engineering and Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Search for more papers by this authorProfessor Tzyy-Sheng Jason Horng
Department of Electrical Engineering and Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan
Search for more papers by this authorSummary
This chapter discusses the hierarchy of interconnection in ball grid array (BGA). The combination of eutectic bumps and the organic (FR4)-based manufacturing processes are sound in thermal hierarchy, and thus, become mass production technology. The chapter focuses on the introduction to Level 1 interconnection, and gap in FC-PBGA interconnection, and Level 0.5 interconnection. It presents discussion on the changing dynamics in business for more Moore (MM) and more than Moore (MTM), as a result of new through silicon via (TSV) interconnection technology. The chapter also discusses the changing semiconductor business dynamics. It summarizes the metallization used in silicon and III-V compound semiconductors for wirebond and flip chip interconnections. The chapter shows that aluminum pads only exist on silicon, Gold (Au) pads only exist on III-V, and Copper (Cu) can exist on both silicon and III-V compound semiconductor integrated circuits (IC).
References
- Torstein Gleditsch, Helge Kristiansen, and Dag Ausen, “ Chapter F: Multi-Chip Modules,” The Nordic Electronics Packaging Guideline, see http://extra.ivf.se/ngl/F-MCM/ChapterF2.htm#F2
- Kilby and Noyce invented monolithic principle and planar process, respectively, which create electronic devices and components using semiconductors (e.g., silicon and germanium) and semiconductor processes, leading to the brave new world of miniaturization. They are considered as co-inventors of Integrated Circuits (ICs). Kilby won the Nobel Prize in 2000; but, Noyce did not. Noyce died in 1990, and Nobel prizes are not awarded posthumously.
- “ Interconnections: silicides” EE 311 class notes by Prof. Sarawsat, Stanford.
- K. C. Saraswat and F. Mohammadi, “Effect of scaling of interconnection on the time delay of VLSI circuits,” IEEE Journal of Solid-State Circuits, SC- 17(2), April 1982, pp. 275–280.
- Robert H. Havemann, “ Cu/low k Interconnect Technology for 32 nm and Beyond,” Fudan University International Interconnect Symposium, May 28, 2008.
- Robert H. Havemann and James A. Hutchby, “High-Performance Interconnects: An Integration Overview,” Proceedings of the IEEE, 89(5), May 2001.
- K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration,” Proc. IEEE, 89(5), May 2001, pp. 602–633.
- “ 2005 ITRS/ORTC product technology and economic trends,” 2005 ITRS Conference, December 2005, Seoul, Korea.
- P. Kapur, J. P. McVittie, and K. C. Saraswat. “Technology and Reliability Constrained Future Copper Interconnects – Part I: Resistance Modeling, IEEE Trans. Electron Dev., 49(4), April 2002, pp. 590–597.
- Kapur, G. Chandra, J. P. McVittie, and K. C. Saraswat. “Technology and Reliability Constrained Future Copper Interconnects – Part II: Performance Implications,” IEEE Trans. Electron Dev., 49(4), April 2002, pp. 598–604.
- Michael Quirk and Julian Serda, “ Semiconductor Manufacturing Technology,” First Edition, Prentice Hall, 2000.
- “ Scaling of Interconnections,” EE 311 class notes by Prof. Sarawsat, Stanford.
- Jiang Tao, Nathan W. Cheung, and Chenming Hu, “Electromigration characterisitcs of copper interconnects,” IEEE Electron Device Letters, 14(5), May 1993.
- As mentioned in “ IBM 100 – Copper Interconnects: The evolution of microprocessors,” copper (Cu) interconnection was first introduced by IBM, with assistance from Motorola, in 1997. Compared to Al (aluminum), Cu has lower resistivity. Resistance to electromigration of Cu, is significantly better than that of Al. From the above-mentioned reasons, chip can be made smaller, and performs better. Because of the lack of volatile property, Cu could not be patterned using photoresist masking and plasma etching techniques that had been successfully applied with Al. Additive patterning, also known as a “Damascene” or “dual-Damascene” process by analogy to an ancient technique of metal inlaying, was developed for Cu. In this process, the underlying silicon oxide insulating layer is patterned with open trenches where the conductor should be. A thick coating of copper that significantly overfills the trenches is deposited on the insulator, and chemical-mechanical planarization (CMP) is used to remove the Cu (known as overburden) that extends above the top of the insulating layer. The Cu that has been sunken in the trenches of the insulating layer is not removed and becomes the patterned metallization. Damascene processes generally form and fill a single feature with Cu per Damascene stage. Dual-Damascene processes generally form and fill two features with Cu at once, for example, a trench overlying a via may both be filled with a single Cu deposition using dual-Damascene.
- Jeff Gambino, Fen Chen, and John He, “ Copper interconnect technology for the 32 nm node and beyond,” IEEE Custom Integrated Circuits Conference (CICC), 2009.
- Xuefeng Zhang et al., “ Chip-Package Interaction and Reliability Impact on Cu/Low-k Interconnects,” Chapter 2, 2008, available https://www.ae.utexas.edu/~ruihuang/papers/CPI2008.pdf
- Don Frye and Carol Mohler, “Low K & Ultra Low K, Metrology comes to the rescue,” International Conference on Characterization and Metrology for ULSI Technology, March 16, 2005.
-
Agnes M. Padovani et al., “Porous methylsilsequioxane for Low-k dielectric applications,” Electrochemical and Solid-State Letters, 4(11), 2001, pp. F25–F28.
10.1149/1.1403215 Google Scholar
- Y. Lin et al., “Subcritical delamination of dielectric and metal films from low-k OrganoSilicate Glass (OSG) thin films in bufferered pH solutions,” Materials Research Society (MRS) Symposium, 795, 2004.
- X. Zeng et al., “ Wafer level bump technology for III-V MMIC manufacturing,” CS MANTECH Conference, Portland, OR, USA, May 17-20, 2010.
- Kezia Cheng, “ Copper interconnect on GaAs pHEMT by evaporation process,” CS MANTECH Conference, Tampa, Florida, USA, May 18-21, 2009.
- Steve Kilgore et al., “ Electromigration of electroplated gold interconnects,” MRS Symposium, 863, 2005.
- “ User guide for GaAs MMIC storage, pick & place, die attach, and wire bonding,” United Monolithic Semiconductors, France, February 2001.
- Edward Y. Chang et al., “Hybrid dry-wet chemical etching process for via holes for gallium arsenide MMIC manufacturing,” IEEE Trans. On Semiconductor Manufacturing, 1(4), November 1988, pp. 157–159.
- Vanita R. Agarwal, D. S. Rawal, and H. P. Vyas, “Review: Back-side via hole etching process for grounding GaAs based monolithic microwave integrated circuits,” Journal of the Electrochemical Society, 152(7), G567–G576 (2005).
- “Micro drill ‘via holes’ in III-V semiconductors,” III-V Review, 18(5), June-July 2005, pp. 40–41.
- Barry C. Johnson, “ Overview of Chip-Level Packaging,” in Electronic Materials Handbook, Vol. 1 Packaging, Merrill L. Minges, ed., ASM International, November 1989.
- Pradeep Lall, Shantanu Deshpandc, and Luu Nguyen, “ Principal compoents regression model for prediction of acceleration factors for copper-aluminum wirebods subjected to harsh environments,” ECTC, Las Vegas, NV, USA, May 31- June 3, 2016.
- Rent's IBM internal memoranda published in IBM J. Res. & Dev. Vol. 49, No. 4/5 July/September 2005, pp. 777–803.
- “ Cu Pillar and BOT Flip Chip Technology,” SPIL, see, http://www.spil.com.tw/technology/?u=4. Note: BOT stands for “Bump On Trace” technology.
- Venkatesh Sundaram, “ Advances in Electronic Packaging Technologies by Ultra-small Microvias, Super-fine Interconnections and Low Loss Polymer Dielectrics,” doctoral dissertation, Ga Tech, May 2009.
- Ivy Qin et al., “ Wire bonding looping solutions for advanced high pin count devices,” ECTC, Las Vegas, NV, USA, May 31-June 3, 2016.
- “ Electronic Packaging and Interconnection Technology,” Lecture 4, Herzog, UFSC (Federal University of Santa Catarina), 2007.
- Ultra fine pitch wire bonding can be found from Kulicke & Soffa website, http://www.kns.com/en-us/Pages/Ultra%20Fine%20Pitch%20Wire%20Bonding.aspx?kns=PXq%2fP99ocYzE60GSJgLlB88xfoCFzlDv
- “ TI's journey ro high-volume copper wire bonding production,” Texas Instruments, October 2014.
- Liao Jun Kai et al., “ Silver alloy wire bonding,” ECTC 2012.
- The intermetallics have different properties than the individual metals (in this discussion, Au and Al). The intermetallics formed between the two individual metals which may cause problems in wirebonding. The main compounds formed are Au5Al2 (white plague) and AuAl2 (purple plague), which both form at high temperatures. When the intermetallic layers are formed, it may induce reduction in the volume, which leads to cavities in the metals near the interface. Also, the intermetallic itself may be brittle, and is likely to have a lower conductivity. These properties may cause performance degradation, or electrical failure in the long run.
- George Harman, Wire Bonding in Microelectronics – Materials, Processes, Reliability, and Yield, McGraw-Hill, NY, 1997.
- Bob Chylak et al., “Next Generation Nickel-based Bond Pads Enable Copper Wire Bonding,” ECS Transactions, 18(1), 2009, p. 777–785.
- Horst Clauberg, Petra Backus, and Bob Chylak, “ Nickel-palladium bond pads for copper wire bonding,”Microelectronics Reliability, 2010.
- Yi Heang Chen, Meiying Hsiao, and Chiu E Tseng, “ The properties comparison between Au and Cu wires bond in DRAM component,” IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), July 2011.
- Electroless Nickel plating, PacTech GmbH, 2014, http://www.pactech.com/index.php?option=com_content&view=article&id=34&Itemid=74
- Lester W. Herron, Raj N. Master, and Rao R. Rummala, “ Method of making multilayered glass-ceramic structures having an internal distribution of copper-based conductors,” U.S. Patent 4,224,367, Novembr 18, 1980.
- R. R. Tummala, J. U. Knickerbocker, S. H. Knickerbocker, L. W. Herron, R. W. Nufer, R. N. Master, M. O. Neisser, B. M. Kellner, C. H. Perry, J. N. Humenik, and T. F. Redmond, “High-performance glass-ceramic/copper multilayer substrate with thin-film redistribution,” IBM Journal of Research and Development, 36(5), September 1992.
- UBM is the structure that is used to accommodate the flip chip bumps. It is constructed on the top of I/O pads of an IC. Depending on the metal of the final I/O pads (Al, Cu, or Au), the UBM constructions can be varied.
- “ Chip bonding at the first level,” Chapter 9 in “Roadmaps of Packaging Technology,” Eric Bogatin, editor, Integrated Circuit Engineering Corporation, 1997, from http://smithsonianchips.si.edu/ice/cd/PKG_BK/CHAPT_09.PDF.
- “ Bumping Design Guide,” FC International, May 2009.
- Shinji Ishikawa et al., “ Lead-free solder micro-ball bumps for the next generation of flip chip interconnection: micro-ball materials, bump formation process and reliability,” ECTC, 2007.
- Tanno et al., “ Method and apparatus for loading solder balls,” U.S. Patent 8,091,766 B2, January 10, 2012.
- Kengo Aoya, “ Micro-ball loading device and loading method,” U.S. Patent 8,434,664 B2, May 7, 2013.
- TC Chai et al., “ Impact of packaging design on reliability of large die Cu/low-k (BD) interconnect,” ECTC 2008.
- Xiaowu Zhang et al., “ Development of through silicon via (TSV) interposer technology for large die (21x21mm) fine-pitch Cu/low-k FCPBGA package,” ECTC 2009.
- Seung Wook Yoon et al., “ UBM integrity studies on copper/low-k dielectrics for fine pitch flip chip packaging,” ECTC 2003.
- John Lau, “ TSV Manufacturing Yield and Hidden Costs for 3D IC Integration,” ECTC 2010.
- N. Ranganathan et al., “ Integration of high aspect ratio tapered silicon via for through-silicon interconnection,” ECTC 2008.
- Yasuhiro Morikawa et al., “ A novel scallop free TSV etching method in magnetic neutral loop discharge plasma,” ECTC 2012.
- Yasuhiro Morikawa et al., “ Total cost effective scallop free Si etching for 2.5D & 3D TSV fabrication technologies in 300 mm wafer,” ECTC 2013.
- Meng-Jen Wang et al., “ TSV technology for 2.5D IC solution,” ECTC 2012.
- Yasuhiro Morikawa et al., “ Novel TSV process technologies for 2.5D/3D packaging,” ECTC 2014.
- Yu-Jen Chang et al., “ Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer,” ECTC 2012.
- Kuan-Chung Lu et al., “ Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/High-speed applications,” ECTC 2012.
- Kuan-Chung Lu and Tzyy-Sheng Horng, “ Wideband and scalable equivalent-circuit model for differential Through Silivcon Vias with measurement verification,” ECTC 2013.
- Karthik Chandrasekar et al., “ System and circuit level powe modeling of energy-efficient 3D-stacked Wide I/O DRAMs,” DATE13, European Design Automation Association (EDAA) 2013.
- J. Kim et al., “A 1.2 V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4_128 I/Os using TSV-based stacking,” IEEE JSSC, 47(1), 2012.
- Mikael Detalle et al., “ Interposer Technology for high band width interconnect applications,” ECTC 2013.
- Kei Murayama et al., “ Warpage control of silicon interposer for 2.5D package application,” ECTC 2013.
- Pei-Jer Tzeng et al., “ Process integration of 3D Si interposer with double-sided active chip attachment,” ECTC 2013.
- C. Neher, R.L. Lander, A. Moskaleva, J. Pasner, M. Tripathi, and M. Woods, “ Further developments in gold-stud bump bonding,” Topical Workship on Electronics for Particle Physics 2011, September 26-30, 2011.
- W. Reinert and T. Harder, “ Performance of the stud bump bonding (SBB) process in comparison to silder flip chip technology,” IEEE 2000.
- Ying-Hui Wang and Tadatomo Suga, “ 20-µm-pitch Au micro-bump interconnection at room temperature in ambient air,” ECTC 2008.
- Yotaro Yasu et al., “ Investigation of optimized high-density flip chip interconnect design including micro Au bumps and underfill for ultrabroadband (DC-40 GHz) applications,” Electrical Design of Advanced Packaging and System, EDAPS 2012.
- “ Fine pitch Copper pillar flip chip,” Amkor Technology, http://www.amkor.com/go/Copper-Pillar-Flip-Chip
- Hou-Jun Hsu, Jung-Tang Huang, Pen-Shan Chao, and Sheng-Hsiung Shih, “ A novel process for fabricating ultra-high coplanarity in electroplating lead-free copper pillar bump,” available from NTUT website, http://www.cc.ntut.edu.tw/~wwwoaa/oaa-nwww/oaa-bt/bt-data/97_phd/paper/14.pdf
- “ IC Advanced Packaging Technology,” PPT presentation, Carl Chen, 2009.
- Olaf van der Sluis et al., “Efficient damage sensitivity analysis of advanced Cu/low-k bond pad structures by means of the area release energy criterion,” Microelectronics Reliability, 47(12), December 2007.
- Integrated Circuits refer to active devices and passives components that are fabricated on a same monolithic semiconductor platform. The concept was proposed by Jack Kilby and Robert Noyce. Kilby and Noyce invented monolithic principle and planar process, respectively, which create electronic devices and components using semiconductors (for example, silicon and germanium) and semiconductor processes, leading to the brave new world of miniaturization. They are considered as co-inventors of integrated circuits (ICs). Kilby won the Nobel Prize in 2000; but, Noyce did not. Noyce died in 1990, and Nobel prizes are not awarded posthumously.
- Annual gross profit margins for Intel: http://ycharts.com/companies/INTC/gross_profit_margin
- Annual gross profit margins for Amkor: http://ycharts.com/companies/AMKR/gross_profit_margin
- “ 3D packaging,” Newsletter on 3D IC, TSV, WLP, and Embedded Technologies, 13, December 2009.
- Scott Jewler, “ TSV MEOL: End of the middle, or middle of the end?” Chip Scale Review, July/August 2012.
- http://electroiq.com/insights-from-leading-edge/2012/08/
-
Joachim N. Burghartz, editor. Ultra-thin Chip Technology and Applications. Springer, Germany, 2011.
10.1007/978-1-4419-7276-7 Google Scholar
