Complete delay modeling of sub-threshold CMOS logic gates for low-power application

In this paper, the propagation delay of a complementary metal-oxide semiconductor (CMOS) inverter circuit in sub-threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub-threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub-threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub-threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub-threshold circuit in sub-90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.