A dividing ratio changeable digital PLL based on phase state memory and double clock-edge detection

In this paper, we propose a dividing ratio changeable digital phase-locked loop (PLL) based on phase state memory and double clock-edge detection that satisfies the three characteristics of low jitter, wide lock-in range, and fast pull-in at the same time. The counter for the double edge detection of the base clock reduces the circuit scale by using a selector. In the steady state, the output jitter of the proposed digital PLL is always a half pulse width of the base clock regardless of the frequency fluctuation of the base clock. Also, the upper bound frequency of the lock-in range becomes six times that of the conventional dividing ratio changeable PLL, when the permissible output jitter is identical. Furthermore, the fast pull-in is finished in one cycle of the input signal and the pulse width of the multiplication output signal becomes almost constant. © 2010 Wiley Periodicals, Inc. Electron Comm Jpn, 93(9): 19–26, 2010; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.10251