A modified circuit for symmetric and asymmetric multilevel inverter with reduced components count
Corresponding Author
Kishor Thakre
Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India
Correspondence
Kishor Thakre, Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India.
Email: [email protected]
Search for more papers by this authorKanungo Barada Mohanty
Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India
Search for more papers by this authorAditi Chatterjee
Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India
Search for more papers by this authorVinaya Sagar Kommukuri
Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India
Search for more papers by this authorCorresponding Author
Kishor Thakre
Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India
Correspondence
Kishor Thakre, Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India.
Email: [email protected]
Search for more papers by this authorKanungo Barada Mohanty
Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India
Search for more papers by this authorAditi Chatterjee
Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India
Search for more papers by this authorVinaya Sagar Kommukuri
Electrical Engineering Department, National Institute of Technology Rourkela, Rourkela, India
Search for more papers by this authorSummary
This article investigates a modified circuit for multilevel converter based on cascaded basic units. The proposed circuit can be operated in both symmetrical and asymmetrical source configuration. The magnitudes of two dc source in basic units can be adopted for symmetrical and asymmetrical configuration. In the symmetrical configuration, the magnitude of the dc voltage source is identical for each unit. On the other hand, the values of the dc voltage source for basic units are unequal in asymmetrical configuration. In order to generate a large number of voltage levels with less number of components, several methods are suggested for determining the magnitude of dc voltage source. Comparison analysis proves that the suggested circuit needs less number of components, reduces power loss, and improves the efficiency of the inverter. Moreover, the standing voltage across the switches is acceptable compared with contemporary topologies. Simulation and experimental results for 15-, 17-, 23-, and 31-level inverters are analysed to validate the performance of investigated topology.
REFERENCES
- 1Leon JI, Kouro S, Vazquez S, et al. Multidimensional modulation technique for cascaded multilevel converters. IEEE Trans Ind Electron. 2011; 58(2): 412-420.
- 2Rodriguez J, Bernet S, Wu B, Pontt JO, Kouro S. Multilevel voltage source-converter topologies for industrial medium-voltage drives. IEEE Trans Ind Electron. 2007; 54(6): 2930-2945.
- 3Buccella C, Cecati C, Cimoroni MG, Razi K. Analytical method for pattern generation in five-level cascaded H-bridge inverter using selective harmonic elimination. IEEE Trans Ind Electron. 2014; 61(11): 5811-5819.
- 4Cecati C, Ciancetta F, Siano P. A multilevel inverter for PV systems with fuzzy logic control. IEEE Trans Ind Electron. 2010; 57(12): 4115-4125.
- 5Sivakumar K, Das A, Ramchand R, Patel C, Gopakumar K. A five-level inverter scheme for a four-pole induction motor drive by feeding the identical voltage-profile windings from both sides. IEEE Trans Ind Electron. 2010; 57(8): 2776-2784.
- 6Baker RH, Bannister LH. Electric power converter. U.S. Patent3867643A, Feb. 1975.
- 7Nabae A, Takahashi I, Akagi H. A new neutral-point-clamped PWM inverter. IEEE Trans Ind Appl. 1981; 1A-17(5): 518-523.
- 8Yuan X, Barbi I, Stemmler H. A new diode clamping multilevel inverter, IEEE/APEC, pp. 494-501, 1999.
- 9Roshankumar P, Rajeevan PP, Mathew K, Gopakumar K, Leon JI, Franquelo LG. A five-level inverter topology with single-DC supply by cascading a flying capacitor inverter and an H-bridge. IEEE Trans Power Electron. 2012; 27(8): 3505-3512.
- 10Meynard TA, Foch H, Forest F, et al. Multicell converters: derived topologies. IEEE Trans Ind Electron. 2002; 49(5): 978-987.
- 11Veenstra M, Rufer A. Control of a hybrid asymmetric multilevel inverter for competitive medium-voltage industrial drives. IEEE Trans Ind Appl. 2005; 41(2): 655-664.
- 12Babaei E, Hosseini SH. New cascaded multilevel inverter topology with minimum number of switches. Energ Conver Manage. 2009; 50(11): 2761-2767.
- 13Laali S, Abbaszades K, Lesani H. A new algorithm to determine the magnitudes of dc voltage sources in asymmetrical cascaded multilevel converters capable of using charge balance control methods, in Proc. ICEMS, Incheon, Korea, pp. 56-61, Oct. 2010.
- 14Kangarlu MF, Babaei E, Laali S. Symmetric multilevel inverter with reduced components based on non-insulated dc voltage sources. IET Power Electron. 2012; 5(5): 571-581.
- 15Babaei E, Kangarlu MF, Mazgar FN. Symmetric and asymmetric multilevel inverter topologies with reduced switching devices. Electr Pow Syst Res. 2012; 86: 122-130.
- 16Oskuee MRJ, Khalinasab S, Najafi RS. Reduction of circuit devices in developed symmetrical/asymmetrical multilevel inverter. J Circuit Syst Comp. 2016; 25(4):1650020.
- 17Thakre K, Mohanty KB, Kommukuri VS, Chatterjee A. New topology for asymmetrical multilevel inverter: an effort to reduced device count. J Circuit Syst Comp. 2018; 27(4):1850055.
- 18Oskuee MRJ, Salary E, Najafi RS. Creative design of symmetric multilevel converter to enhance the circuit's performance. IET Power Electron. 2015; 8(1): 96-102.
- 19Banaei MR, Salary E. Verification of new family for cascaded multilevel inverter switch reduction of components. J Electr Eng Technol. 2011; 6(2): 245-254.
- 20Banaei MR, JannatiOskuee MR, Khounjahan H. Reconfiguration of semi-cascaded multilevel inverter to improve systems performance parameters. IET Power Electron. 2014; 7(5): 1106-1112.
- 21Gupta KK, Jain S. Comprehensive review of a recently proposed multilevel inverter. IET Power Electron. 2014; 7(3): 467-479.
- 22Ajami A, Oskuee MRJ, Khosroshahi MT, et al. Cascade multi-cell multilevel converter with reduced number of switches. IET Power Electron. 2014; 7(3): 552-558.
- 23Kangarlu MF, Babaei E, Sabahi M. Cascaded cross-switched multilevel inverter in symmetric and asymmetric conditions. IET Power Electron. 2013; 6(6): 1041-1050.
- 24Haque MT. Series sub-multilevel voltage source inverters (MLVSIs) as a high quality MLVSI, in Proc. SPEEDAM, pp. F1B-1–F1B-4, 2004.
- 25Babaei E, Hosseini SH, Gharehpetian GB, Haque MT, Sabahi M. Reduction of DC voltage sources and switches in asymmetrical multilevel converters using a novel topology. J Power Syst Res. 2007; 77(8): 1073-1085.
- 26Babaei E. A cascade multilevel converter topology with reduced number of switches. IEEE Trans Power Electron. 2008; 23(6): 2657-2664.
- 27Ebrahimi J, Babaei E, Gharehpetian GB. A new multilevel converter topology with reduced number of power electronic components. IEEE Trans Ind Electron. 2012; 59(2): 655-667.
- 28Oskuee MRJ, Karimi M, Ravadanegh SN, Gharehpetian GB. An innovative scheme of symmetric multilevel voltage source inverter with lower number of circuit devices. IEEE Trans Ind Electron. 2015; 62(11): 6965-6973.
- 29Samadaei E, Gholamian S, Sheikholeslami A, Adabi J. An envelope type (E-type) module: asymmetric multilevel inverters with reduced components. IEEE Trans Ind Electron. 2016; 63(11): 7148-7156.
- 30Alishah RS, Nazarpour D, Hosseini SH, Sabahi M. Reduction of power electronic elements in multilevel converters using a new cascade structure. IEEE Trans Ind Electron. 2015; 62(1): 256-267.
- 31Thakre K, Mohanty KB. Comparative analysis of THD for symmetrical and asymmetrical 17 level cascaded H-bridge inverter using carrier based PWM techniques, in proc. Industrial Instrumentation and Control (ICIC), 2015 International Conference on, May 2015, India, pp. 306–310.
- 32Gupta KK, Jain S. A novel multilevel inverter based on switched DC sources. IEEE Trans Ind Electron. 2014; 61(7): 3269-3278.
- 33Farokhnia N, Fathi SH, Salehi R, Gharehpetian GB, Ehsani M. Improved selective harmonic elimination pulse-width modulation strategy in multilevel inverters. IET Power Electron. 2012; 5(9): 1904-1911.
- 34Dahidah MSA, Agelidis VG. Selective harmonic elimination PWM control for cascaded multilevel voltage source converters: a generalized formula. IEEE Trans Power Electron. 2008; 23(4): 1620-1630.
- 35Ahmed I, Borghate VB. Simplified space vector modulation technique for seven-level cascaded H-bridge inverter. IET Power Electron. 2014; 7(3): 604-613.
- 36Leon JI, Portillo R, Franquelo LG, Vazquez S, Carrasco JM, Dominguez E. New Space Vector Modulation Technique for Single-Phase Multilevel Converters, 2007 IEEE international symposium on industrial electronics, Vigo, 2007, pp. 617-622.
- 37Leon JI, Vazquez S, Watson AJ, Franquelo G, Wheeler P, Carrasco JM. Feed-forward space vector modulation for single-phase multilevel cascaded converters with any DC voltage ratio. IEEE Trans Ind Electron. 2009; 56(2): 315-325.
