Vertical GaN Transistor with Semi-Insulating Channel
Abstract
Herein, vertical GaN transistors with a semi-insulating (SI) 1.3 μm thick channel layer and C doping of 1 × 1017 cm−3 are studied. Structures are grown using a metal–organic chemical vapor deposition on conductive GaN substrates. SI GaN is sandwiched between 2.5 μm thick n-GaN drift layer (Si doping of ≈ 1 × 1017 cm−3) and a top n-GaN contact layer. A circular mesa region with a diameter of 180 μm is patterned using a deep dry etching. The gate contact formed on the mesa sidewall is insulated from the vertical channel using a 20 nm thick Al2O3 grown by an atomic layer deposition. Despite a robust layout, transistors transfer characteristics indicate normally off behavior if extracted from the linearly scaled current–voltage characteristics and an open channel drain current of 30 mA at the gate bias of 4 V. Achieved on/off ratio is 107 at −2 V subthreshold gate bias when the full channel depletion is reached. And, 200 ns long gate pulse characteristics show only a marginal trapping even though no post-metallization annealing is performed. By comparing experimental results with modeling, mobility of free electrons in the channel is found to be about 45 cm2 V−1 s−1.
Conflict of Interest
The authors declare no conflict of interest.
Open Research
Data Availability Statement
The data that support the findings of this study are available from the corresponding author upon reasonable request.
