Characterization of Ultrathin Fully Depleted Silicon-on-Insulator Devices Using Subthreshold Slope Method

2.1 Short Review of the Previous Studies

In this section, after a brief review of the previous relevant publications, we will present our modifications to the method for characterization of interface traps in HKMG SOI FETs. The first publication reporting a possibility of application of STS measurements for estimation of interface trap densities,^[13] known to the current authors, appeared in 1975. The authors^[13] demonstrated that interface states, located near the channel, strongly influence the subthreshold slope of I_D(V_G) dependence at small drain voltages for an MOS transistor working in weak inversion. Later it was shown that for thin-film SOI MOSFETs (a laser-recrystallized Si film on oxidized Si wafer was investigated) the STS is also affected by the properties and interface states located near the back gate.^[14] Introduction of bonded SOI wafers and their application in MOSFET technology intensified the research on the influence of interface traps on STS (see refs. [15-19] and references therein). In these publications, a relation of the STS to the interface traps was proved, and expressions for estimation of interface trap densities from the STS measurement results were proposed.

The buried density of interface traps (D_IB) for FDSOI MOSFETs was evaluated in ref. 14. The method was based on a dual-gate (DG) voltage sweep in the subthreshold region. Namely, the STS was measured while both the FG and BG were swept with voltages changing according to a ratio k = V_BG/V_FG, with k = 0…10. By neglecting the D_IF, i.e., the interface trap density at the FG, an average value for D_IB can be derived using this approach.

Experimental results for carrier mobility and STS in HKMG SOI MOSFETs with various gate lengths obtained at various temperatures (77–300 K) were presented by Pham-Nguen et al.^[20] It was shown that for short gates (L_Ch≤ 100 nm), mobility is nearly independent of the temperature. The detection limit for a sum of states from both interfaces (D_IF + D_IB) was estimated for the direct extraction of interface state density from STS measurements as ≈10¹² eV⁻¹ cm⁻².^{[20, 21]}

Three methods for D_IF,_IB evaluation in HKMG SOI MOSFETs, i.e., front-channel swing, back-channel swing, and coupling effect, were compared in ref. 22. From those methods,the subthreshold swing results for the back-channel were affected by the D_IF most of the others. However, the authors^[22] conclude that the sensitivity of the method may not be sufficient for MOSFETs with a thin buried oxide.

The publication that triggered our interest in the STS measurement method promised extraction of D_IF(E_IT) and D_IB(E_IT) distributions for FDSOI MOSFETs.^[10] The authors of ref. 10 used a similar DG operation approach to that presented in ref. 9; however, the expression for STS was applied to fit the experimental STS(I_D) data measured for three different k = V_BG/V_FG values. Measurements for three k values were used for an iterative extraction procedure of C_IF and C_IB dependences on, respectively, the front- and back-surface potentials. Finally, the surface potentials were related to the energy location of the trap level in the Si bandgap responsible for D_IF,IB = C_IF,IB/q interface trap density (q presents an electron charge). We were unable to repeat the success of the authors^[10] for two reasons. First, extraction of STS(I_D) data by the expression for the swing for such a broad I_D range is questionable due to the substantial impact of the regular current itself. Second, the number of unknown variable parameters substantially exceeds the possible fitting accuracy. For us, the procedure used in ref. 10 was not clearly described. Unfortunately, there were no follow-up publications related to these results.

Recently, the STS measurement method was applied for D_IT (E_IT) estimation in SOI FD FinFETs.^[11] The results indicate that the trap density can be extracted between E_it–E_V ∼ 0.65–0.90 eV. The D_IT(E_IT) is extracted with a minimum amount of modeling, the strongest requirement being that short-channel effects can be neglected in the device under study. The expressions presented in ref.12 provide an accurate description of the STS as a function of the main FDSOI stack parameters and interface trap density in single-gate operation mode.

In our opinion, the concept of optimal coupling (OC) in DG operation mode, used for D_IB estimation in ref. 9, seemed not fully explored. For optimal coupling, such a value for the ratio $k_{\text{OC}}={(V_{\text{BG}}/V_{\text{FG}})}_{\text{OC}}$ in DG operation is selected experimentally that both front- and back-surface potentials increase at the same rate with the applied FG voltage. Our approach for estimation of D_IF,IB(E_IT) dependences from STS measurements is based mainly on the theory and calculations presented in the previous publications (see refs. [9-11, 15] and references therein). Where possible, we will refer to the previously published equations to avoid lengthy and cumbersome expressions related to the complexity of the system under consideration.

2.2 Subthreshold Swing for HKMG SOI FET

In subthreshold range, the I_D(V_FG), with I_D as drain current and V_FG FG voltage, dependence is usually represented by a plot of log(I_D) versus V_FG for V_DS (drain-source bias) significantly exceeding thermal voltage U_T= k_BT/q. Such a representation is related to the expression for I_D(V_FG) (see, e.g., ref. 5) leading to a linear dependence with a slope of [ln(10)nU_T]⁻¹. Here, q is the electron charge, n > 1 is a nonideality factor that reflects the presence of the interface traps, k_B is the Boltzmann constant, and T is temperature. By STS, we designate the reverse of the slope. The theoretical limit for this value (i.e., for n = 1) is STS_Th = ln(10)U_T. Therefore, for the nonideality factor, we have n = STS_M/STS_Th, where STS_M is the experimentally measured slope.

Therefore, if the capacitances related to the oxides and Si channel are known, measurements of n and k_OC using the procedure described in ref. 9 and application of the aforementioned calculations give a possibility to estimate $C_{\text{IB}}$, $C_{\text{IF}}$ values and consequently D_IF,IB = C_IF,IB/q trap densities averaged for the measured subthreshold region.

Instant modifications in design and fabrication processes for microelectronic devices require measurements of actual FET stock parameters. The actual values for C_OF, C_OB, and C_Si may differ from what is expected because of the actual fabricated thickness of layers and their real content/structure. Therefore, for getting accurate results for D_IF,IB it will be advantageous to determine the stack parameters of the devices under study (DUT) experimentally. As it was noted previously, CV measurements for single FET devices with dimensions in the 10–100 nm range cannot be performed due to the low signal/noise ratio. Therefore, special structures containing hundreds of devices connected in parallel are usually applied for this purpose. A review of the measurement methods applied for the determination of the FET stack parameters can be found in ref. 1. Among others, the full-split CV (FSCV) method^{[23, 24]} supplies all the information necessary for further application in the STS measurement procedure. This method was applied in our measurements to obtain capacitance values for the layers in the FET stack.

It also appears necessary to include a concept of “dark space”^[25] in consideration of the equivalent oxide thicknesses (EOT) and, consequently, the capacitances of the stack layers in the FET. This concept was applied in the FSCV method^[23] as well and reflects the fact that for nanometric oxide thicknesses the thickness associated with quantum effects (depletion of free carriers at the semiconductor surface) becomes the same order of magnitude as the measured oxide thicknesses. We used the standard value for dark-space thickness in silicon, i.e., ≈1.2 nm,^[26] at both front and back Si channel interfaces. The relevant “dark-space” capacitors should be taken into account for calculations of the C_IF,IB.

2.3 Temperature Dependence for STS

Measurements of the STS from an FET at a single temperature and estimation of the stack parameters by the FSCV method provide the averaged D_IF,IB values ($\overline{D}$_IF,IB) for an energy level in the Si channel bandgap determined by the values of temperature and bias on the gate(s). A variation of measurement temperature and the related change in the STS measurement parameters supply information about trap densities at different energy level positions in the Si bandgap. Therefore, measurements at several temperatures (multi-T measurements) will characterize density distributions of interface traps D_IF,IB(E_IT).

Large variation of measurement temperature is rarely used in semiconductor device characterization because it requires a special technique capable of controlling the sample temperature in a broad range and exceeds possibilities of standard probe stations. This is the reason that publications where FET characterization is studied under various temperatures (especially below 250 K) are scarce (see, e.g., ref. [20, 27-31]). On the other hand, control of the STS by temperature in combination with the gate bias is the best way of probing the energy distribution of interface traps at small-gate-bias conditions, where the current in the channel is mainly controlled by the carriers excited from the interface traps. An attempt to extract D_IF,IB at various measurement temperatures for an FDSOI FET was presented in ref. 32. However, as the estimations were based on a simple model,^[33] the presented results are questionable.

Determination of energy levels of traps, participating in STS, from biasing conditions and temperature also present a nontrivial task. For an “ideal” or, at least, for well-defined FET structures, the trap energy level participating in STS (i.e., the difference between the Fermi level position and energy of the Si valence band) can be obtained either using commercially available Poisson–Schrodinger equation solvers (PSESs; see, e.g., ref. 34 and references therein) or using a freely available band energy diagram program for complex multilayer dielectric devices.^[35] For real devices, only approximate parameters are usually known; therefore, the application of these programs has limitations. We will use a simple approximation, which will give some scatter in energy position but still will reflect the D_IF,IB(E_IT) distributions semiquantitatively.

Subsequently we will present procedures necessary for obtaining interface trap density distributions for FG and BG from STS measurements in the temperature range 120–400 K. In the formalism, we will follow recent and detailed description of band structure/bias relationships for FDSOI FETs that can be found in ref. 37 and estimations used in ref. 11.

Equation (19) is valid for measurement in STS mode at temperature T and contains the unknown term ${\mathrm{\Delta \varphi }}_{\text{FG}}(T)$. The ratio g_mU_T/I_D is determined experimentally from I_D(V_FG) STS measurements at the smallest possible I_D values. $\Delta E_{\text{FG}}(T)$ is calculated for a given T using the band energy diagram program for complex multilayer dielectric devices.^[36] To account for the specific structure of the gate oxide of a device in the calculations,^[36] we can use the EOT data estimated for the front and back oxides in FSCV measurements. The same measurement/calculation procedure may be applied for the BG ΔE_BG(T) as well.

3.1 Samples

The DUT were ultra-thin-body and BOX (UTTB) n-type FDSOI MOSFETs provided by GlobalFoundries and were produced using 22 nm node technology.^[2] They were fabricated on (100) SOI wafers with highly scaled BOX and silicon channel thickness. For the characterization experiments, samples not showing top performance were chosen. The gate stack consisted of a high-k gate dielectric on top of a SiON interfacial layer, with an equivalent front oxide thickness EOT ≈ 1 nm and a TiN metal gate (SG devices). As a variation, devices with an additional thin SiO₂ layer atop the channel (with equivalent front oxide thickness EOT ≈3 nm, EG devices) were also investigated. The BOX thickness in both cases was ≈20 nm. The devices applied for the STS measurements were standard FET structures with a rectangular channel and four separated contacts for the FG, BG, source (S), and drain (D). The channel length of the FETs was L_CH = 100 nm and channel width W_CH = 150 nm. For capacitance measurements, 144 FETs connected in parallel (three contacts: FG, BG, S + D), with dimensions L_CH = W_CH = 2 μm each were applied. Therefore, the total area of structures used in CV measurements was 576 μm². The sketches of the measurement setups are shown in Figure 1a,b. The chips containing DUTs for STS and CV measurements were separated from the 8 in. wafer to be attached by thermoconductive glue on an electrically isolated sample holder.

3.2 Setup

The sample holder with a sample attached was placed inside the PS-100 model probe station (Lake Shore) allowing measurement at cryogenic temperatures under vacuum conditions. A range of temperatures from 120 to 400 K was used in the measurements. Cooling of the sample stage was done by cryogenic N₂ flow. Control and regulation of the temperature of the sample stage and the thermal shield, surrounding the sample stage, was performed using a “Lake Shore model 336” temperature controller with ± 0.5 K accuracy.

Electrical contact to the pins of a DUT was accomplished using four micromanipulated stages equipped with probe arms and 25 μm “continuously variable temperature probes” with tungsten tips. The whole electric circuitry was assembled using triaxial cables. A microscope (7:1 zoom), equipped with a CCD camera, light source, and monitor, was used for observation of the sample during contacting. During measurements, the sample was protected from outside illumination.

Electrical measurements were performed using a B1500A semiconductor Device Analyzer (Agilent) equipped with four 100 mA/100 V, 10 fA/0.5 μV resolution medium power source/monitor unit (SMU) modules and a multifrequency capacitance measurement unit. Measurements were performed using specially designed measurement routines written in the frame of the EasyEXPERT software installed on the B1500 setup.

4.1 Results for the Samples

The results of I_D(V_GF, k, T) measurements for EG sample are shown in Figure 2a for three temperature values (i.e., for 200, 300, and 400 K) and eight k values at each temperature (for k = 0 to 3 with step 0.5 and for k_OC). The I_D (V_GF, k_OC, T) dependencies are shown with solid lines for each T. The range of I_D, where data for the $\overline{D}$_IF,IB estimations are collected, is shown in Figure 2a by an arrow. Obtained STS(I_D) dependencies for k = k_OC values at three temperatures are shown in Figure 2b. The solid lines in Figure 2b show the fitted curves according to Equation (17). The interval between short vertical lines shows the range of I_D used for D_IF,IB(E_IT) estimations in multi-T characterization mode.

The results obtained for the SG and EG samples for FSCV + STS measurements at 300 K are included in Table 1. These results were obtained using measurement procedures similar to those described in refs. [9, 23, 37] and applying calculations presented in Section 3.1. The obtained EOT parameters of the stacks well correspond to those expected.

Since the multi-T STS measurements are presented for the first time here, we will give more details on the data-processing procedures subsequently, together with the obtained results of the measurements. Because a set of the STS measurements at a single temperature and different k values is followed with the measurement at the optimal coupling conditions (k_OC), where the increase in potential is equal for the BG and FG, we can apply that data for ΔE_BG(T) and ΔE_FG(T) estimation. Moreover, for the k = k_OC conditions n = g_mU_T/I_D ≈1 and the $\Delta E_{\text{BG}}(V_{\text{FG}})$ dependence simplifies further. For the back gate, the actual bias at k = k_OC will be V_BG = V_FGk_OC+ V_DS/2. It is also important to note that in Equation (19) the g_m/I_D ratio is contained; therefore, the actual distribution of the current in the channel, i.e., the value for α (see Section 2.2), is not essential for these energy calculations. To simplify the temperature dependence further, we can set the source–drain voltage V_DS as a multiple of U_T for each measurement temperature (see Equation (17)). We set V_DS = 3U_T in our experiments. Such a low V_DS value prevents the emergence of such short-channel effects as the drain-induced barrier lowering and hot-carrier injection.

The trap density distributions are further calculated using the STS measured at optimal coupling conditions for each temperature. As before, we use data with the smallest currents from the sets here. Usually, eight to ten g_m/I_d values are averaged from the acceptable level of the signal-to-noise ratio in I_d (V_FG) measurements. These values are used in the calculation of the corresponding E_IT from Equation (19) and D_IF,IB(E_IT) trap densities using the procedure presented in Section 2.2. The values for the ${\mathrm{\Delta \varphi }}_{\text{FG}}$ can be found using a similar program to that presented in ref. 36.

Distributions of trap densities for EG and SG samples are shown in Figure 3a,b respectively. In the same figure, the levels of average interface trap densities measured at 300 K are also shown in the left part of the figures for comparison.

4.2 Discussion

The aim of the this article is describing an updated characterization method of HKMG FDSOI FETs; therefore, we will discuss the obtained results for the FETs only briefly. Interestingly, the interface trap densities for the FG and BG in the case of EG DUT are almost equal, whereas in the case of SG DUT, this parameter for the FG is approximately three to four times larger in comparison to the BG of the same FET. It can be supposed that growth of additional silicon oxide at the FG suppresses the FG interface states, but causes an increase in the density of interface states at BOX. It should be noted that charge pumping measurements on similar samples with large gate areas also showed an increased density of interface states in the case of the EG DUT.

Comparison of D_IT(E_IT) dependences for FG and BG interfaces in the EG and SG samples with the averaged $\overline{D}$_IF,IB levels (see Figure 3a,b and Table 1) shows the significant advantage of the multi-T measurements. Namely, for the SG DUT it appears that elevated trap density exists at ≈E_V + 0.9 eV, which is suppressed in the EG DUT. Contrarily, D_IT significantly increases to the center of the midgap in the case of the FG interface of the EG sample. This may correspond to the formation of P_b1-(AOD) interface states (see, e.g., ref. 40 and references therein) during the formation of the oxide near the GF in the EG sample. Interestingly, the level of defect density at the BG interface is substantially increased in the EG sample in comparison to that in the SG; however, the U-shape of the D_IBG(E_IT) dependence looks similar. Moreover, the peak in the D_IBG(E_IT) distribution between 1 and 1.1 eV also repeats in both samples.

4.3 Possible Applications of the Method and Limitations

The methodology described in Section 2.1 and 2.2 can be applied for characterization of FDSOI FET FG and BG interface trap densities in three different modes. Considering the purpose of the characterization, we can label those modes as a “monitoring,” “verification,” and “design” modes.

For relatively fast, even in-line, monitoring of product quality, the STS measurements under various k = V_BG/V_FG (e.g., 0–3 with step 0.5) and at a single temperature (e.g., for T = 300 K) should be performed and the value for k_OC should be determined following the procedure described in ref. 9. After that, the averaged values for D_IF and D_IB can be determined using Equation (5)–(9). For this method, some preassumed or previously established parameters for the FET stack can be used. The limitations for this method are apparent. 1) The obtained trap densities strongly depend on the correctness of the used stack parameters. 2) The densities are averaged for a significant and generally unknown range of E_IT. 3) All the stack parameters except trap densities are supposed to maintain the same values from sample to sample.

A more detailed check of the FET parameters can be accomplished, adding FSCV measurements prior to the STS monitoring mode. In this mode, first, the actual parameters of the stack are obtained using measurement procedures explained in refs. [32, 37] Further, these parameters are used for correct estimation of averaged trap density values in the monitoring mode. Therefore, intentional or unintentional process variations for samples may be tracked and analyzed. This possibility comes at the price of extended measurement time and fabrication of a particular group of structures for FSCV measurements inside every wafer or even every chip.

For the design of a newer/modified fabrication process, the detailed check may be augmented by STS measurements at several temperatures in the range 120–400 K (multi-T measurements). Such a study will provide distributions of interface trap densities at the FG and BG interfaces and will supply values for essential parameters of the stack, giving possibilities for modeling of the structure and finding possible ways for future improvements. These measurements require much longer time and, at least at present, require cutout of the chip from the wafer for effective temperature control during the test at low temperatures.

Next, we would like to formulate once more the limitations and assumptions that were used in the method. During our estimations, we assumed that carrier mobility in the channel in the applied regime and for the applied DUT dimensions is nearly independent of the measurement temperature following ref. 20. Moreover, we assumed that the fixed charges located in the front oxide are not affected by the change in temperature. It was also supposed that interface trap distributions are smooth enough in a way that for a small change in surface potential we can assume them to be nearly constant. The calculations are applicable only for the FD case when the effect of the depletion charge on the current in the channel can be ignored; i.e., the gate potential does not affect the charge and surface potential fluctuations caused by doping can be ignored. The DUTs are working out of the short-channel regime, and the V_DS value significantly exceeds the thermal voltage. To avoid admixing of regular inversion channel current in the STS, only values of current slightly exceeding the noise values should be used in estimations.

The exact sensitivity limit and limitations related to the quality of an FET for the method are still to be established. From our preliminary tests, the method shows reliable results at the gate leakage under 1 mA cm⁻² and for D_IF and D_IB levels below 5×10¹² eV⁻¹ cm⁻². We should also remind the reader that for FETs with L_ch > 100 nm the supposition about the independence of the carrier mobilities from the temperature will not be correct and may cause misinterpretation of the obtained STS data. It should also be noted that because expression (19) for E_IT contains actual parameters of the FET (i.e., EOT, k_OC, n, and ${\mathrm{\Delta \varphi }}_{\text{FG}}$), the range of trap energies tested by measurement and the necessary energy resolution cannot be defined a priori. However, after obtaining the preliminary data (e.g., for the temperature range 120–450 K with a step 25 K), the FET can be remeasured at the specific temperatures.