This paper presents a novel single-phase 37-level asymmetrical multilevel inverter with fewer components and less voltage stress at the switches which reduces the cost of the inverter and increases efficiency. Existing multilevel inverters utilize a higher number of components to provide better output quality which increases the cost and the complexity. The proposed inverter circuit generates 37 levels of output voltage by utilizing only four DC sources and thirteen IGBT switches. Reduction of the total harmonic distortion (THD) and improvement of the output quality of the proposed structure are performed by implementing the half-height modulation technique. The number of components, cost factor, THD, and efficiency of the proposed structure have been compared to those of the inverter structures that are currently in use. The performance of the proposed structure is evaluated by MATLAB/Simulink and simulation results show that the proposed circuit produces higher-level output voltage with reduced THD by utilizing less components/levels and low-rated devices which makes the proposed topology cost-effective and efficient compared to other existing topologies. Also, the proposed structure offers stable performance under a variety of load conditions. Multiple input sources and less distorted output of the proposed topology make it appropriate for renewable energy generating systems which contribute to the reliable, efficient, and sustainable generation of electricity.

1. Introduction

In the growth of sustainable and reliable power systems, multilevel inverter (MLI) technology is essential as it meets the demands of power electronics’ applications. A MLI is such an inverter technology which produces an output voltage in the form of AC by taking several DC voltage levels at its input. By providing high-quality AC voltage with reduced harmonic distortion, MLIs become applicable in renewable energy systems [1], uninterruptible power supply systems [2], electric vehicles (EVs), high-voltage motor drives, and grid-tied inverters for distributed power generation [3]. Despite several advantages, conventional MLIs require a large number of components while producing more level of voltage at the output and face challenges related to switching losses, harmonic distortion, and higher stress on switches, which increases cost, reduces efficiency, and thus creates a hindrance to providing better performance for modern power systems [4, 5]. To overcome these issues, many research studies are being performed for meeting the requirements of diverse applications.

Flying capacitor (FC), neutral point clamped (NPC), and cascaded H-bridge (CHB) MLIs are the three commonly used conventional MLI topologies [6]. Of these, the CHB MLI structure has the additional advantage of not requiring any clamping diodes or capacitors and it provides high output voltage by cascading several single-phase converter modules which are simple in modular architecture [7]. CHB MLIs are categorized into two types viz. symmetrical and asymmetrical CHB MLIs. Symmetrical CHB MLIs possess the same magnitudes of the DC voltage sources, whereas asymmetrical CHB MLIs have unequal magnitudes of the DC voltage sources [8]. Besides this, in the case of asymmetrical CHB MLIs, the magnitude of the DC voltage sources can be selected in accordance with the need of achieving higher voltage levels [9]. While implementing a MLI structure, it is necessary to use a lower number of semiconductor devices for generating a higher level of voltage, which reduces the circuit complexity and thus increases the inverter’s reliability.

A single-phase asymmetrical MLI structure has been demonstrated in [10] for medium voltage application which uses twelve unidirectional switches and three DC sources for producing 23 levels of output voltage. However, employing additional gate driver circuits and switches brings about a rise in the inverter circuit’s cost. In [11], the presented topology is an asymmetric 21-level MLI which consists of ten unidirectional switches and three power sources. According to the required voltage level, it uses more switches and its switches also experience high-voltage stress due to the high total standing voltage (TSV) which are the disadvantages of this topology. Optimal utilization of the switching devices and voltage sources helps to simplify these issues. The authors in reference [12] present a new 17-level asymmetrical MLI which is applicable to photovoltaic systems. This MLI circuit has ten switches and four DC sources and 40% of its switches experience maximum voltage stress, which increases the inverter’s cost. Besides this, the total harmonic distortion (THD) of the output voltage is also high, that is, 7.78%. In [13], a novel 17-level CHB asymmetrical MLI architecture is described. It creates 17 different levels of output voltage through the use of two bidirectional and twelve unidirectional switches and four capacitors and four DC sources. However, the usage of more number of total components results in an increase in the inverter circuit’s cost. The same problem of increased cost for the use of more components while producing lower output voltage also exists in topologies [14, 15]. A 17-level MLI is built in [16] with an emphasis on component reduction and voltage boosting via switched-capacitor methods. Although the topology provides justifiable performance, its usefulness for high-voltage applications is limited by its greater THD (4.85%) and TSV (4.5 pu). Some MLIs which produce higher voltage levels at the output with less switches are presented in [17, 18]. These topologies use less switches while producing higher output voltage, so they are cost-effective for the usage of lower switches, but in [17], the output voltage has more harmonic contents with 2.53% of THD, and in [18], the topology of the switches experiences higher voltage stress. References [19–36] explore several new MLI circuits that utilize fewer switches and DC sources to provide a higher output voltage with lower THD, and the switches used in these circuits experience lower TSV. Modulation techniques such as unipolar trapezoidal pulse width modulation (PWM), carrier overlapping (CO), phase disposition (PD), alternative phase opposition and disposition (APOD), variable frequency (VF), and altered carrier PWM have been studied in various topologies [37, 38]. These approaches aim to reduce harmonics but often require complex control and are less scalable for high-level inverters, emphasizing the need for more simple and adaptable techniques. Self-balanced capacitor voltages, inherent voltage gain, and single DC source operation are some of the benefits of switched-capacitor MLIs (SC-MLIs) [39, 40]. However, these benefits come with significant challenges. Due to its high inrush current and current stress on switches and capacitors, SC-MLIs are only suitable for low- or medium-power applications. This results in higher power losses. To address inrush currents, additional components such as inductors are used, but this raises switching losses and overall circuit complexity [39]. Furthermore, under different load situations, performance decreases and complex control methods are needed to maintain capacitor voltage balance [40]. Although SC-MLIs are effective in certain applications, further study is required to develop inverter topologies that can operate efficiently at higher power ratings and with reduced switching losses. As the existing solutions do not meet the requirements of developing technologies, so novel MLI topologies are required to create higher output voltage with less components, reduced THD, and lower TSV. These features will decrease the cost of the MLIs and make it more efficient.

A novel 37-level asymmetrical MLI circuit is presented and designed in this work. The proposed topology uses lower components per level for generating higher output voltage with reduced THD, lower switching loss, and enhanced efficiency. Also, the proposed topology’s switches experience lower voltage stress which makes the inverter circuit cost-effective. MATLAB/Simulink is employed to simulate the proposed MLI structure. To assess the effectiveness of the proposed structure, its features are contrasted with those of a few other topologies. EVs and renewable energy generating systems find the proposed MLI convenient.

The rest of the paper is organized as follows. Section 2 describes the designed structure of the developed 37-level MLI circuit with design equations, its switching states, and modulation techniques. Features of the proposed MLI structure, voltage stress on switches, efficiency calculation, dynamic load variation effects and cost function determination are discussed in Section 3. In Section 4, a comparison of the proposed structure with a few existing structures and the detailed explanations of the graphical representations of the comparative analysis are presented. The application of the proposed topology is stated in Section 5. Finally, in Section 6, the conclusion and future scope are stated.

2. Proposed Inverter Circuit Configuration

While designing the proposed 37-level MLI, various parameters should be considered to ensure the desired system’s performance, reliability, and efficiency. The proposed 37-level asymmetrical MLI circuit is shown in Figure 1, which consists of thirteen IGBT switches and four DC voltage sources. Among them, eleven switches, S₁, S₂, S₅, S₆, S₇, S₈, S₉, S₁₀, S₁₁, S₁₂, and S₁₃, are unidirectional and two switches, S₃ and S₄, are bidirectional. This proposed 37-level MLI circuit can generate a stepped output waveform with 37 distinct voltage levels. With a V_DC value of 22.22 V, the magnitudes of the DC sources, V1, V2, V3, and V4, are chosen in the proportion of 1:3:7:7 for the purpose of producing the required amount of output power. Under these circumstances, the proposed inverter circuit is capable of producing 18 positive voltage levels from +V_DC to + 18 V_DC, zero voltage level, and 18 negative voltage levels from −V_DC to − 18 V_DC.

Details are in the caption following the image — **Figure 1**
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Proposed 37-level multilevel inverter circuit.

2.1. Switching States of Operation of the Proposed Topology

MLIs operate in several switching states to produce the necessary output voltage waveform depending on the exact needs of the application. In this proposed 37-level asymmetrical inverter topology, there are thirty-seven operating states to generate 37 levels of output voltage. Table 1 shows switches’ switching patterns for producing different output voltage levels. The state value “1” indicates the conduction state of the switches, whereas the state value “0” specifies the nonconduction state. Based on the gate signals, six IGBT switches turn on each time, which are connected to respective voltage sources to create the different voltage levels.

Table 1. Pattern of switching for the proposed 37-level MLI structure.

	S₁	S₂	S₃	S₄	S₅	S₆	S₇	S₈	S₉	S₁₀	S₁₁	S₁₂	S₁₃	V_out
Positive levels	1	0	0	0	1	0	0	1	1	1	0	1	0	18 V_DC
	1	0	0	0	1	1	0	0	1	1	0	1	0	17 V_DC
	1	0	0	0	1	1	0	0	1	0	1	1	0	16 V_DC
	1	0	0	0	1	0	1	1	0	1	0	1	0	15 V_DC
	1	0	0	0	1	1	1	0	0	1	0	1	0	14 V_DC
	1	0	0	0	1	1	1	0	0	0	1	1	0	13 V_DC
	1	0	0	0	1	0	1	1	0	1	0	0	1	12 V_DC
	1	0	1	0	0	0	0	1	1	1	0	1	0	11 V_DC
	1	0	1	0	0	1	0	0	1	1	0	1	0	10 V_DC
	1	0	1	0	0	1	0	0	1	0	1	1	0	9 V_DC
	1	0	1	0	0	0	1	1	0	1	0	1	0	8 V_DC
	1	0	1	0	0	1	1	0	0	1	0	1	0	7 V_DC
	1	0	1	0	0	1	1	0	0	0	1	1	0	6 V_DC
	1	0	1	0	0	0	1	1	0	1	0	0	1	5 V_DC
	0	0	0	1	1	0	0	1	1	1	0	1	0	4 V_DC
	0	0	0	1	1	1	0	0	1	1	0	1	0	3 V_DC
	0	0	0	1	1	1	0	0	1	0	1	1	0	2 V_DC
	0	0	0	1	1	0	1	1	0	1	0	1	0	1 V_DC
	0	0	0	1	1	1	1	0	0	1	0	1	0	0

Negative levels	1	1	0	0	0	0	0	1	1	0	1	0	1	0
	0	1	0	1	0	1	1	0	0	0	1	0	1	−1 V_DC
	0	1	0	1	0	0	1	1	0	0	1	0	1	−2 V_DC
	0	1	0	1	0	0	1	1	0	1	0	0	1	−3 V_DC
	0	1	0	1	0	1	0	0	1	0	1	0	1	−4 V_DC
	0	1	0	1	0	0	0	1	1	0	1	0	1	−5 V_DC
	0	1	0	1	0	0	0	1	1	1	0	0	1	−6 V_DC
	0	1	0	1	0	1	0	0	1	0	1	1	0	−7 V_DC
	0	0	1	1	0	1	1	0	0	0	1	0	1	−8 V_DC
	0	0	1	1	0	0	1	1	0	0	1	0	1	−9 V_DC
	0	0	1	1	0	0	1	1	0	1	0	0	1	−10 V_DC
	0	0	1	1	0	1	0	0	1	0	1	0	1	−11 V_DC
	0	0	1	1	0	0	0	1	1	0	1	0	1	−12 V_DC
	0	0	1	1	0	0	0	1	1	1	0	0	1	−13 V_DC
	0	0	1	1	0	1	0	0	1	0	1	1	0	−14 V_DC
	1	1	0	0	0	1	1	0	0	0	1	0	1	−15 V_DC
	1	1	0	0	0	0	1	1	0	0	1	0	1	−16 V_DC
	1	1	0	0	0	0	1	1	0	1	0	0	1	−17 V_DC
	1	1	0	0	0	1	0	0	1	0	1	0	1	−18 V_DC

The proposed inverter system generates 37-level output voltages from −18 V_DC to + 18V_DC. The proposed 37-level MLI’s switching states define which IGBT switches and voltage sources are active to create particular output voltages from −18 V_DC to + 18V_DC. In each switching state, the current flow path can be determined by the connected voltage sources and the active switches. The IGBT switches include body diodes, which allow current to flow forward even when the switches are switched off. This enables smooth current flows and makes the switch protection possible, especially for circuits with inductive loads. In addition to providing a path channel for this current, the body diode protects from dangerous spikes that may damage the components. In this way, the body diode maintains the inverter functioning consistently.

Table 2 specifies the different states of switching for each switch with a load current flowing path. Among all the switching states, eight switching states are explained as follows.

Table 2. Switching states for the proposed 37-level asymmetrical MLI.

Switching states	Load current flow path	Output voltage
State-1	S₅ − V₃ − V₄ − S₁ − S₁₀ − V₁ − S₈ − Load − S₉ − V₂ − S₁₂	18 V_DC
State-2	S₅ − V₃ − V₄ − S₁ − S₁₀ − S₆ − Load − S₉ − V₂ − S₁₂	17 V_DC
State-3	S₅ − V₃ − V₄ − S₁ − S₁₁ − V₁ − S₆ − Load − S₉ − V₂ − S₁₂	16 V_DC
State-4	S₅ − V₃ − V₄ − S₁ − S₁₀ − V₁ − S₈ − Load − S₇ − S₁₂	15 V_DC
State-5	S₅ − V₃ − V₄ − S₁ − S₁₀ − S₆ − Load − S₇ − S₁₂	14 V_DC
State-6	S₅ − V₃ − V₄ − S₁ − S₁₁ − V₁ − S₆ − Load − S₇ − S₁₂	13 V_DC
State-7	S₅ − V₃ − V₄ − S₁ − S₁₀ − V₁ − S₈ − Load − S₇ − V₂ − S₁₃	12 V_DC
State-8	S₃ − V₄ − S₁ − S₁₀ − V₁ − S₈ − Load − S₉ − V₂ − S₁₂	11 V_DC
State-9	S₃ − V₄ − S₁ − S₁₀ − S₆ − Load − S₉ − V₂ − S₁₂	10 V_DC
State-10	S₃ − V₄ − S₁ − S₁₁ − V₁ − S₆ − Load − S₉ − V₂ − S₁₂	9 V_DC
State-11	S₃ − V₄ − S₁ − S₁₀ − V₁ − S₈ − Load − S₇ − S₁₂	8 V_DC
State-12	S₃ − V₄ − S₁ − S₁₀ − S₆ − Load − S₇ − S₁₂	7 V_DC
State-13	S₃ − V₄ − S₁ − S₁₁ − V₁ − S₆ − Load − S₇ − S₁₂	6 V_DC
State-14	S₃ − V₄ − S₁ − S₁₀ − V₁ − S₈ − Load − S₇ − V₂ − S₁₃	5 V_DC
State-15	S₅ − S₄ − S₁₀ − V₁ − S₈ − Load − S₉ − V₂ − S₁₂	4 V_DC
State-16	S₅ − S₄ − S₁₀ − S₆ − Load − S₉ − V₂ − S₁₂	3 V_DC
State-17	S₅ − S₄ − S₁₁ − V₁ − S₆ − Load − S₉ − V₂ − S₁₂	2 V_DC
State-18	S₅ − S₄ − S₁₀ − V₁ − S₈ − Load − S₇ − S₁₂	1 V_DC
State-19	S₅ − S₄ − S₁₀ − S₆ − Load − S₇ − S₁₂	0
State-20	S₁ − S₂ − S₁₃ − S₉ − Load − S₈ − S₁₁	0
State-21	S₁ − S₂ − S₁₃ − S₉ − Load − S₆ − V₁ − S₁₁	−1 V_DC
State-22	S₁ − S₂ − S₁₃ − V₂ − S₇ − Load − S₈ − V₁ − S₁₀	−2 V_DC
State-23	S₁ − S₂ − S₁₃ − V₂ − S₇ − Load − S₈ − S₁₁	−3 V_DC
State-24	S₁ − S₂ − S₁₃ − V₂ − S₇ − Load − S₆ − V₁ − S₁₁	−4 V_DC
State-25	S₄ − V₃ − S₃ − S₁₂ − V₂ − S₉ − Load − S₆ − V₁ − S₁₁	−5 V_DC
State-26	S₄ − V₃ − S₃ − S₁₃ − S₉ − Load − S₈ − V₁ − S₁₀	−6 V_DC
State-27	S₄ − V₃ − S₃ − S₁₃ − S₉ − Load − S₈ − S₁₁	−7 V_DC
State-28	S₄ − V₃ − S₃ − S₁₃ − S₉ − Load − S₆ − V₁ − S₁₁	−8 V_DC
State-29	S₄ − V₃ − S₃ − S₁₃ − V₂ − S₇ − Load − S₈ − V₁ − S₁₀	−9 V_DC
State-30	S₄ − V₃ − S₃ − S₁₃ − V₂ − S₇ − Load − S₈ − S₁₁	−10 V_DC
State-31	S₄ − V₃ − S₃ − S₁₃ − V₂ − S₇ − Load − S₆ − V₁ − S₁₁	−11 V_DC
State-32	S₄ − V₃ − V₄ − S₂ − S₁₂ − V₂ − S₉ − Load − S₆ − V₁ − S₁₁	−12 V_DC
State-33	S₄ − V₃ − V₄ − S₂ − S₁₃ − S₉ − Load − S₈ − V₁ − S₁₀	−13 V_DC
State-34	S₄ − V₃ − V₄ − S₂ − S₁₃ − S₉ − Load − S₈ − S₁₁	−14 V_DC
State-35	S₄ − V₃ − V₄ − S₂ − S₁₃ − S₉ − Load − S₆ − V₁ − S₁₁	−15 V_DC
State-36	S₄ − V₃ − V₄ − S₂ − S₁₃ − V₂ − S₇ − Load − S₈ − V₁ − S₁₀	−16 V_DC
State-37	S₄ − V₃ − V₄ − S₂ − S₁₃ − V₂ − S₇ − Load − S₈ − S₁₁	−17 V_DC
State-38	S₄ − V₃ − V₄ − S₂ − S₁₃ − V₂ − S₇ − Load − S₆ − V₁ − S₁₁	−18 V_DC

1^st Switching state: S₁, S₅, S₈, S₉, S₁₀, and S₁₂ switches are kept active, while the remaining switches are left off during the first switching state. To provide an output of 18V_DC, V₁, V₂, V₃, and V₄ voltage sources are also active with the switches S₁, S₅, S₈, S₉, S₁₀, and S₁₂. Figure 2(a) shows the current circulation path for this state.

5^th Switching state: S₁, S₅, S₆, S₇, S₁₀, and S₁₂ switches are kept active, while the remaining switches are left off during the fifth switching state. To provide an output of 14V_DC, V₃ and V₄ voltage sources are also active with the switches S₁, S₅, S₆, S₇, S₁₀, and S₁₂. Figure 2(b) shows the current circulation path for this state.

14^th Switching state: S₁, S₃, S₇, S₈, S₁₀, and S₁₃ switches are kept active, while the remaining switches are left off during the 14^th switching state. To provide an output of 5V_DC, V₁, V₂, and V₄ voltage sources are also active with the switches S₁, S₃, S₇, S₈, S₁₀, and S₁₃. Figure 2(c) shows the current circulation path for this state.

18^th Switching state: S₄, S₅, S₇, S₈, S₁₀, and S₁₂ switches are kept active, while the remaining switches are left off during the 18^th switching state. To provide an output of 1V_DC, V₁ voltage source is also active with the switches S₄, S₅, S₇, S₈, S₁₀, and S₁₂. Figure 2(d) shows the current circulation path for this state.

19^th Switching state: S₄, S₅, S₆, S₇, S₁₀, and S₁₂ switches are kept active, while the remaining switches are left off during the 19^th switching state. As no voltage source is active with S₄, S₅, S₆, S₇, S₁₀, and S₁₂ switches, there is no available path for the input voltage, so the output is zero. Figure 2(e) shows the current circulation path for this state.

25^th Switching state: S₃, S₄, S₆, S₉, S₁₁, and S₁₂ switches are kept active, while the remaining switches are left off during the 25^th switching state. To provide an output of −5V_DC, V₁, V₂, and V₃ voltage sources are also active with the switches S₃, S₄, S₆, S₉, S₁₁, and S₁₂. Figure 2(f) shows the current circulation path for this state.

34^th Switching state: S₂, S₄, S₈, S₉, S₁₁, and S₁₃ switches are kept active, while the remaining switches are left off during the 34^th switching state. To provide an output of −14V_DC, V₃ and V₄ voltage sources are also active with the switches S₂, S₄, S₈, S₉, S₁₁, and S₁₃. Figure 2(g) shows the current circulation path for this state.

38^th Switching state: S₂, S₄, S₆, S₇, S₁₁, and S₁₃ switches are kept active, while the remaining switches are left off during the 38^th switching state. To provide an output of −18 V_DC, V₁, V₂, V₃, and V₄ voltage sources are also active with the switches S_2, S₄, S₆, S₇, S₁₁, and S₁₃. Figure 2(h) shows the current circulation path for this state.

The typical 37-level staircase output waveform and the respective gate pulses are shown in Figure 3.

2.2. Design Equations of the Proposed 37-Level MLI Structure

A 37-level MLI structure is ingeniously designed to produce an output power of better quality while minimizing the number of components required. One of the standout features of this type of MLI is its ability to generate highly refined output with reduced THD, better voltage quality, and enhanced efficiency. The MLIs’ high-quality output power is essential to the systems that generate renewable energy. Various MLI topologies have some individual unique equations for representing their operation. These equations help in the determination of a number of components such as switches, sources, and gate driver circuits, which are essential to fulfill the necessary performance requirements.

For the designed MLI circuit, the required number of IGBT switches can be found by using the following equation:

()

Equation (2) can be used to compute the required number of DC sources for the proposed MLI as

()

Equation (3) can be used to calculate the necessary number of gate driver circuits as

()

The proposed MLI’s maximum output voltage can be obtained via the following equation:

()

where N_L represents the output voltage level’s number of proposed MLI which is 37. So, design equations are essential to easily find the different parameters of the MLIs, which ensures that the proposed topology fulfills the desired performance, reliability, and efficiency criteria.

2.3. Modulation Technique

MLIs generate higher-level output voltage waveforms by using multiple levels of DC voltage. The half-height modulation technique is employed for creating output signals with low harmonic components for the proposed MLI structure. In this technique, a reference sine wave is generated and adjusted by fine-tuning the modulation index (MI) to ensure that the peak value of the reference sine wave is precisely half of the DC voltage level to minimize distortion. In order to control the inverter switches properly which are represented in Tables 3, 4, 5, and 6, the output waveform is then split into four quadrants for an entire cycle (0–360°) and switching angles are calculated by using the formulas [20] of equations (5)–(8) for each section. Finally, the gate pulses are applied to the inverter, which combines the DC voltage levels to produce a low-distortion AC output waveform that closely matches the reference sine wave. The entire process of the half-height modulation technique, including the calculation of switching angles, gate pulse generation, and output waveform creation, is illustrated in the flowchart shown in Figure 4.

Table 3. Switching angles for the first quadrant.

Symbol	Angle
A₁	1.592
A₂	4.780
A₃	7.984
A₄	11.212
A₅	14.478
A₆	17.792
A₇	21.168
A₈	24.624
A₉	28.179
A₁₀	31.855
A₁₁	35.685
A₁₂	39.709
A₁₃	43.983
A₁₄	48.590
A₁₅	53.664
A₁₆	59.442
A₁₇	66.444
A₁₈	76.464

Table 4. Switching angles for the second quadrant.

Symbol	Angle
A₁₉	103.536
A₂₀	113.556
A₂₁	120.558
A₂₂	126.336
A₂₃	131.410
A₂₄	136.017
A₂₅	140.291
A₂₆	144.315
A₂₇	148.145
A₂₈	151.821
A₂₉	155.376
A₃₀	158.832
A₃₁	162.208
A₃₂	165.522
A₃₃	168.788
A₃₄	172.016
A₃₅	175.220
A₃₆	178.408

Table 5. Switching angles for the third quadrant.

Symbol	Angle
A₃₇	181.592
A₃₈	184.780
A₃₉	187.984
A₄₀	191.212
A₄₁	194.478
A₄₂	197.792
A₄₃	201.168
A₄₄	204.624
A₄₅	208.179
A₄₆	211.855
A₄₇	215.685
A₄₈	219.709
A₄₉	223.983
A₅₀	228.590
A₅₁	233.664
A₅₂	239.442
A₅₃	246.444
A₅₄	256.464

Table 6. Switching angles for the fourth quadrant.

Symbol	Angle
A₅₅	283.536
A₅₆	293.556
A₅₇	300.558
A₅₈	306.336
A₅₉	311.410
A₆₀	316.017
A₆₁	320.291
A₆₂	324.315
A₆₃	328.145
A₆₄	331.821
A₆₅	335.376
A₆₆	338.832
A₆₇	342.208
A₆₈	345.522
A₆₉	348.788
A₇₀	352.016
A₇₁	355.220
A₇₂	358.408

In the half-height modulation technique, in order to determine the switching angles, the output waveform is split into four quadrants for an entire cycle (0–360°). Switching angles determined by the half-height modulation technique are represented in Tables 3, 4, 5, and 6. By using the formulas [20] of equations (5)–(8), the switching angles are computed.

Switching angles for the first quadrant (0–90°) can be obtained as

()

where j = 1, 2, 3, 4,…, m − 1/2 and the output voltage levels are expressed by “m.”

Switching angles for the second quadrant (90–180°) can be obtained as

()

Switching angles for the third quadrant (180–270°) can be obtained as

()

Switching angles for the fourth quadrant (270–360°) can be obtained as

()

The gate pulses given to each of the switches to produce the required output through the half-height modulation technique are shown in Figure 5. In order to validate that the proposed circuit can generate 37 levels of voltage at the output, simulation is performed through MATLAB/Simulink using the half-height modulation technique. The voltage and current output waveforms of the proposed MLI circuit, determined by the simulation, are displayed in Figure 6.

3. Features of the Proposed MLI

Assessment of different features of a MLI is necessary while designing the inverter as it ensures that the inverter meets the requirements to function effectively. While assessing the proposed MLI, several features should be taken into consideration such as voltage stress across the switches, efficiency, and cost function of the proposed MLI as these features help to evaluate the overall performance and reliability of the proposed MLI. The following features are used to assess the effectiveness of the MLI.

3.1. Voltage Stress Estimation

To design and optimize a MLI, the knowledge of TSV is crucial, as TSV helps in selecting suitable switches with voltage ratings that can handle the maximum standing voltage, which ensures the reliability and longevity of the inverter and thus contributes to the overall efficiency and cost-effectiveness. TSV also helps in preventing damage to the inverter during abnormal operating conditions. Any inverter circuit’s cost is decreased by reducing the stress across switches.

The TSV is the total of each of the switch’s maximum voltage stresses. There are eleven unidirectional switches (S₁, S₂, S₅, S₆, S₇, S₈, S₉, S₁₀, S₁₁, S₁₂, and S₁₃) and two bidirectional switches (S₃ and S₄) in the proposed MLI circuit.

Each unidirectional switch’s maximum voltage stress is defined as follows:

()

Each bidirectional switch’s maximum voltage stress is defined as follows:

()

The TSV of the designed MLI circuit is determined as follows:

()

For the proposed MLI, the maximum output voltage is calculated as

()

The TSV of the proposed MLI structure is expressed in per unit as follows:

()

The amount of stress distribution can be represented by a term called normalized voltage stress (NVS). NVS refers to the voltage experienced by a component or a switch normalized to a reference value. It is the ratio of the actual voltage stress on a single switch to the maximum voltage stress on any switch in the circuit of a MLI. In the proposed MLI circuit, switch S₁ experiences the maximum voltage stress among all the switches, which is 14 V_DC. Thus, for the proposed MLI circuit, the NVS of all the switches is expressed in Table 7 and the stress distribution on the proposed MLI switches is expressed in Table 8

Table 7. Normalized voltage stress on the proposed MLI switches.

Switches	Voltage stress on each switch	Maximum voltage stress among all the switches	Normalized voltage stress (NVS) calculation	Percentage of stress on switches (%)
S₁	14 V_DC	14 V_DC	14 V_DC/14 V_DC	100
S₂	7 V_DC		7 V_DC/14 V_DC	50
S₃	3.5 V_DC		3.5 V_DC/14 V_DC	25
S₄	7 V_DC		7 V_DC/14 V_DC	50
S₅	7 V_DC		7 V_DC/14 V_DC	50
S₆	1 V_DC		1 V_DC/14 V_DC	7.14
S₇	3 V_DC		3 V_DC/14 V_DC	21.43
S₈	1 V_DC		1 V_DC/14 V_DC	7.14
S₉	3 V_DC		3 V_DC/14 V_DC	21.43
S₁₀	1 V_DC		1 V_DC/14 V_DC	7.14
S₁₁	1 V_DC		1 V_DC/14 V_DC	7.14
S₁₂	3 V_DC		3 V_DC/14 V_DC	21.43
S₁₃	3 V_DC		3 V_DC/14 V_DC	21.43

Table 8. Stress distribution on the proposed multilevel inverter switches.

Stress distribution	Switches	Percentage of switches under stress (%)
Maximum stress	S₁	7.69
Intermediate stress	S₂, S₄ , and S₅	23.08
Minimum stress	S₃, S_6, S_7, S₈, S₉, S₁₀, S₁₁, S₁₂, and S₁₃	69.23

Different voltage stress levels experienced by the switches of the proposed MLI are represented in Figure 7. In this proposed MLI, switches S₆, S₈, S₁₀, and S₁₁ experience the lowest voltage stress among all the switches, which is 1V_DC, and the lowest NVS, which is 7.14%. Switches S₇, S₉, S₁₂, and S₁₃ experience three times greater than the lowest stress among all the switches, which is 3 V_DC, and NVS of 21.43%. The stress on the switch S₃ is 3.5 V_DC with a NVS of 25% which is much less than the intermediate NVS. Switches S₂, S₄, and S₅ experience intermediate voltage stress which is 7 V_DC and NVS of 50% which is exactly half of the maximum voltage stress and maximum NVS. Only one switch of the proposed MLI, S₁, experiences the highest voltage stress of 14 V_DC and a maximum NVS of 100%.

The percentage of switches under different stress levels is represented in Figure 8. The performance of a MLI circuit is greatly affected by the equal stress distribution on the switches, as in this situation, switches operate under similar conditions, which makes more efficient use of power, minimizes loss, and improves overall efficiency. Equal stress distribution on the switches of the MLI also helps to produce an output waveform with low harmonic distortion. So, achieving an equal voltage stress distribution is a key design consideration while designing a MLI. In this proposed MLI, although the voltage stress is not distributed in equal amounts among all the switches, 69.23% of the switches experience minimum voltage stress, 23.08% of switches experience intermediate stress, and only 7.69% of the switches experience high stress.

According to the voltage stress distribution throughout the switches, it is obtained that among the 13 switches of the proposed MLI, 9 switches experience less stress, 3 switches experience intermediate stress, and only one switch experiences maximum stress. The proposed MLI’s reduced voltage stress on switches results in low switching loss and low thermal stress which improves reliability, provides a longer lifespan for the switches, and thus leads to increased system efficiency. Besides this, reduced voltage stress–able switches are low voltage–rated switches, which potentially reduce the overall system cost.

3.2. Efficiency Calculation for Different Loads

Determination of the power losses of the inverter circuit is essential for calculating the efficiency of the MLI. Conduction and switching power losses are the two types of power losses which occur in the MLI topologies. IGBT of the model STGW60V60F is chosen as the power switch, and from the datasheet of the IGBT STGW60V60F, necessary values are obtained for calculating these power losses.

The conduction losses of an IGBT switch can be determined by the formula [25] of equation (14) considering resistive load, and it is calculated as

()

where V_D represents the forward biased voltage drop of the IGBT switch and its value is 0.6 V and R_SW is the on-state switching resistance with a value of 23 mΩ. I (t) is the output current in RMS form and β is a switch specification constant.

Again, the formula [25] of equation (15) can be used to calculate the switching losses of an IGBT switch based on the switching conditions as

()

where V(t) is the output voltage in RMS form, and from the datasheet for thirteen switches, the turn-on delay time, rise time, the turn-off delay time, and fall time are taken as 60 ns, 20 ns, 208 ns, and 14 ns, respectively.

Thus, the total power losses of 13 IGBT switches can be determined by the formula [25] of equation (16) as

()

The formula [25] of equation (17) can be used to calculate the output power of the proposed MLI circuit as

()

Thus, the formula [25] of equation (18) can be utilized to calculate the efficiency of the proposed MLI as follows:

()

For different loads, the determined power loss and efficiency are tabulated in Table 9. With the change of loads, the variations of efficiency are shown in Figure 9. So, the improved efficiency of the proposed topology makes it increasingly attractive for various high-power and high-voltage applications.

Table 9. Proposed MLI’s power loss and efficiency calculations for different loads.

Parameters	Loads
Parameters	R load (100 Ω)	L load (200 mH)	R load (200 Ω)	R-L load (100 Ω-200 mH)
Vrms (V)	282.84	282.84	282.84	282.84
Irms (A)	2.828	4.502	1.414	2.395
Conduction losses, P_C (W)	1.88	3.17	0.894	1.57
Turn on switching loss, E_on (W)	0.005	0.008	0.003	0.004
Turn off switching loss, E_off (W)	0.013	0.021	0.007	0.011
Switching losses, P_S (W)	0.018	0.029	0.01	0.015
Total losses, P_T (W)	24.67	41.59	11.75	20.61
Output power, P_out (W)	799.87	1273.35	399.94	677.40
Input power, P_in (W)	824.54	1314.94	411.69	698.01
Efficiency, η (%)	97.01	96.84	97.15	97.05

3.3. Cost Function Determination

The MLI’s cost function is a key consideration in its design, depending on the specific objectives of the application. Higher voltage level inverters usually require more components, such as switches, capacitors, diodes, and sources, and high voltage–rated devices increase the inverter’s cost. Besides this, the higher-quality components increase reliability and reduce maintenance and replacement costs over the inverters lifecycle. While designing a MLI, it should be taken into account that the inverter generates higher level voltage with less components and low-rated devices so that the reduction of cost of the inverter can be performed. That is why, the determination of cost function is most crucial.

The cost factor of the proposed MLI can be determined by the formula [19] of equation (19) as

()

where N_SW, N_GD, N_DC, N_D, and N_C are the total number of switches, gate driver circuits, DC sources, diodes, and capacitors, respectively, and α is the weight coefficient. Here, the role of the weight coefficient in the determination of the cost factor is important as it shows how the variation in the number of components influences the overall cost.

For the proposed 37-level MLI, considering the weight coefficient α = 0.5 and α = 1.5, the value of cost factor/level is determined as

()

3.4. Dynamic Load Variation Analysis

In order to evaluate the effectiveness of the proposed MLI structure in case of an abrupt load change, a dynamic load variation analysis is necessary. Figure 9 shows the dynamic load variation analysis of the proposed MLI structure. The inverter is initially loaded with a resistive load of R = 100 Ω, and in this condition, the output voltage obtained is 400 V and the output current is 4 A. After a while, the MLI is suddenly loaded with an inductor of value L = 200 mH, and as a result, the MLI feeds an R-L load of 100 Ω and 200 mH, which results in the same output voltage of 400 V, and the load current decreases to 3.38 A as shown in Figure 10(a).

Furthermore, it can be seen from Figure 10(b) that the output voltage stays the same but the current rises to 8 A when the load resistance changes from R = 100 Ω to R = 50 Ω. Consequently, based on these findings it can be said that the proposed MLI structure’s output voltage remains constant even when the load varies. This is advantageous as it ensures a stable and reliable power supply for the connected load, and thus results in high-quality output power and a lower chance of damage to the equipment.

In addition, more dynamic tests for higher frequency applications, variations to the MI, and using nonlinear loads are also performed in order to determine the effectiveness of the proposed inverter. With the change of frequency from 50 Hz to 100 Hz, the output voltage remains the same as shown in Figure 10(c); however, due to the increase of the high-frequency switching losses, the THD of the MLI increases to 1.28%. In order to further investigate the effects of MI fluctuations, simulations with various MI values, ranging from 0.5 to 1.5, are conducted. Initially, the proposed inverter is loaded with a resistive load of R = 100 Ω. Under these conditions, the output voltage and current are 400 V and 4 A, respectively, with a MI of 1 and the THD obtained is 1.09%. With a higher MI of 1.5, the inverter continued to provide high-quality power with an acceptable THD of 1.53%, even though the output voltage (600V) and current (6A) were raised proportionally. Again, the output voltage (200 V) and current (2A) decrease proportionally at a lower MI of 0.5, but the inverter continues to perform well with a little increase in THD of 2.42%. Based on these findings, it can be observed that the proposed MLIs perform consistently over a wide range of MIs as shown in Figure 10(d).

Again, from Figure 10(e), it can be seen that, with the change of load from linear load to nonlinear load (H-bridge diode rectifier), the output voltage waveform remains the same and it does not change its shape, but the shape of the output current waveform changes, which raises the THD (4.87%) due to the nonlinear nature of diode rectifier. As the proposed topology maintains a stable output voltage with low harmonic distortion, it reflects the proposed topology’s effective handling of nonlinear loads. These findings indicate that the proposed MLI is flexible in a variety of operating conditions and it provides excellent power quality despite the effects of changing frequency, MIs, and load conditions.

4. Comparative Analysis With the Existing MLI Topologies

To assess the proposed MLI circuit’s performance and determine whether it meets specific requirements for producing better results, a comparison of it is made with some existing MLI circuits currently in use. Depending on the number of components per voltage level, THD, cost factor per level, TSV, and efficiency, the proposed 37-level MLI structure is compared with several identical output voltage level topologies [27, 29] along with some varying output voltage level asymmetrical MLI topologies [19, 21, 23, 25, 31–36]. Table 10 outlines and displays the comparison variables required to perform a comparative evaluation of the proposed MLI structure with the structures that are currently in use.

Table 10. An analysis comparing the current topologies with the proposed MLI structure.

Topologies	Parameters
Topologies	N_L	N_DC	N_SW	N_GD	N_D	N_C	N_DC/N_L	N_SW/N_L	CC/N_L	THD%	η (%)	TSV (pu)	CF/N_L (α = 0.5)	CF/N_L (α = 1.5)
[31]	21	2	11	11	—	5	0.10	0.52	1.38	3.67	—	—	—	—
[32]	21	3	10	6	2	—	0.14	0.48	1.00	3.99	95.7	2.45	1.06	1.18
[33]	27	3	11	11	2	4	0.11	0.41	1.15	—	97.28	5.3	3.5	4.1
[34]	51	2	8	8	—	—	0.04	0.16	0.35	1.17	96.98	—	—	—
[35]	31	6	10	10	6	—	0.19	0.32	1.03	1.82	—	—	—	—
[36]	31	4	10	10	—	—	0.13	0.32	0.77	—	—	—	—	—
[19]	31	4	14	14	—	—	0.13	0.45	1.03	3.32	92.32	2.4	1.07	1.15
[21]	33	4	12	12	—	—	0.12	0.36	0.85	2.03	94.10	3.31	3.11	3.51
[23]	35	6	12	12	—	—	0.17	0.34	0.86	1.9	—	—	1.74	3.51
[25]	35	5	12	12	—	—	0.14	0.34	0.83	1.88	93.37	3.2	1.6	3.18
[27]	37	6	13	13	—	—	0.16	0.35	0.86	3.64	—	—	—	—
[29]	37	10	12	12	—	—	0.27	0.32	0.92	1.98	97.2	—	—	—
Proposed	37	4	13	13	—	—	0.11	0.35	0.81	1.09	97.01	3.03	0.85	0.93

4.1. Number of Components Per Voltage Level

The number of components while designing a MLI is influenced by the output voltage level that the MLI is required to generate. To generate higher voltage levels, MLIs generally require higher components such as power semiconductor switches, gate drivers, diodes, capacitors, and DC sources. However, the higher number of components with high power–rated devices will make the designed inverters more costly and increase complexity. Figure 11 compares the suggested 37-level MLI with several MLI topologies. The number of components relies on the number of switches, gate drivers, diodes, capacitors, and DC sources. All of these features are taken into consideration while evaluating. The number of voltage levels obtained at the output by various inverter topologies is shown in Figure 11(d).

Table 10 illustrates that the proposed MLI structure utilizes less DC sources per level compared to the current topologies [19, 21, 23, 25, 27, 29, 32, 35, 36], although it produces a higher voltage level at the output, which influences the component count in the inverter, thus resulting in low cost. Although the voltage stress on the switches typically increases when the number of DC sources is reduced, this issue is effectively managed in the suggested circuit by using bidirectional switches. These switches reduce the voltage stress across the switches, which allows the use of low voltage–rated devices, so the cost and complexity are reduced. Although some topologies, such as [33, 36], require fewer sources/levels than the proposed topology, but in [33], switches suffer from high-voltage stress and [36] also introduce challenges related to voltage stress and control complexity by using only 2 DC sources producing 51 voltage level with an EPDB controller. The suggested MLI achieves a higher number of levels while using the same number of DC sources/levels as [32], indicating better utilization of available DC resources. On the other hand, in order to generate the same voltage level [27, 29], there is a need for more DC sources (6 and 10, respectively), whereas the suggested topology requires only 4.

The graphical representations of a number of sources and a number of sources/levels of the inverter topologies are shown in Figures 11(a) and 11(f), respectively.

Again, from Table 10, it can be seen that, while the proposed MLI uses slightly more switches per level than some topologies [23, 25, 29, 34–36], it still uses fewer switches/levels than others [19, 21, 31–33]. Even though the proposed MLI uses more switches per level compared to [23, 25, 29, 35], it requires fewer overall components per level. Besides this, although it [36] utilizes less components per level compared to the proposed topology, it produces a smaller number of voltage levels. On the other hand, although [34] it reduces hardware complexity by using less components while producing higher voltage levels than the proposed topology, using an EPDB controller to produce 51 levels shows challenges related to voltage stress and control complexity, which requires advanced computational resources to manage switching angles. So, the proposed topology is capable of producing higher voltage levels with fewer components, which offers more power without complicating the system.

The graphical representation of the number of switches, number of switches/level, and number of gate drivers of the MLI structure is shown in Figure 11(b), 11(c), and 11(g), respectively.

In order to show the improvements of the proposed design in comparison to the topologies which have comparable or closer output voltage levels such as [21] (33) and [25] (35), it can be found that the proposed topology achieves the highest number of voltage levels (37) while maintaining the same number of DC sources (4) as [21] and fewer than [25] (5). This results in a lower number of DC sources per level (N_DC/N_L = 0.11) compared to [21] (0.12) and [25] (0.14). Again, the proposed structure has switches per level (NSW/NL) of 0.35, which is less than [21] 0.36 and slightly higher than [25] 0.34, but this slight increase is balanced by achieving a reduced number of components per level (CC/N_L = 0.81) compared to both [21] 0.85 and [25] 0.83. These enhancements indicate that the proposed topology is more efficient and less complex than existing topologies [21, 25] which emphasizes the novelty of the proposed MLI.

So, it can be observed from Table 10 that although the proposed MLI has a slightly higher number of switches/levels than some topologies, it requires less components/levels compared to all these existing topologies [19, 21, 23, 25, 27, 29, 31–33, 35] shown in Figure 11(j), which reduces the inverter’s overall cost. Besides this, MLIs with less components per level make the design of the topology simple which contributes to the improved reliability and ease of maintenance.

4.2. THD

The aim of the proposed MLI is to generate such an output voltage waveform which is closer to a sinusoidal waveform which means a waveform with reduced THD. THD is a measure of how much the waveform deviates from a perfect sine wave due to the presence of harmonics. Ideally, the output should be a pure sine wave with only the fundamental frequency, but in reality, inverters often generate additional frequencies known as harmonics. In order to reduce the amplitude of these higher-order harmonics, a half-height modulation technique is used in the proposed circuit which reduces half of the amplitude of the reference waveform. The fundamental frequency’s dominance and the suppression of higher-order harmonics confirm the MLI’s effectiveness in producing high-quality and efficient power, which is vital for renewable energy applications. The harmonic spectrum in Figure 12 demonstrates the effectiveness of the proposed MLI in reducing unwanted harmonics. The spectrum shows that these harmonics are significantly lower in amplitude compared to the fundamental frequency, indicating that the technique is effective and results in a very low THD.

The need for 37 levels in our proposed asymmetrical MLI is to reduce THD and enhance the output waveform’s quality. The MLI with the higher number of voltage level might decrease harmonic distortion, but the actual THD depends on a number of factors, such as operating conditions, component parameter fluctuations, switching strategy, and more. With the same number of levels, different THDs of the MLIs can be obtained due to these factors. In addition, higher-level MLIs would need more components and make the design more complex and increase costs, whereas lower-level MLIs would result in higher THD and decreased power quality. The obtained THD of the proposed topology is compared with other existing topologies [19, 21, 23, 25, 27, 29, 31, 33, 34, 36], and it is obtained that the proposed MLI has the lowest THD value of 1.09%, which is better compared to all others, and is shown graphically in Figure 11(e). Topologies [23, 25] also have comparatively low THD values of 1.9% and 1.88%, respectively, but they still have higher distortion compared to the proposed MLI. Our designed 37-level MLI achieves a significant reduction in THD without requiring additional components as shown in Figure 11(j), which reduces system complexity and cost. Hence, the selection of the 37-level MLIs is appropriate as it provides the best possible balance between reducing THD, controlling system complexity, and maintaining low cost.

4.3. Cost Effectiveness

A MLI should be designed in such a way that it fulfills its required application with reduced cost. The proposed topology has a cost factor per level of 0.85 for a weight coefficient of α = 0.5 and 0.93 for α = 1.5, which is compared with other topologies [19, 21, 23, 25, 32, 33], and it was found to be less costly, which makes the proposed topology economically viable. The graphical representation of the cost factor/level of the inverter topologies is shown in Figure 11(h). Besides this, TSV_pu also influences the cost by determining the voltage stress across switches as the rating of the switches depends on voltage stress. The proposed MLI structure has a TSV_pu value of 3.03, which is less compared to the existing topologies [21, 25, 33], which indicates that the switches of the proposed topology experience lower voltage stress, so low-rated devices can be used; thus, it can be said that the proposed structure is cost-effective. Although the TSV of the proposed topology is more than [19, 32], it utilizes a lower number of components per level while generating 37 levels of output voltage with a reduced cost factor per level. So, in overall considerations, the proposed topology holds better results. The comparison is graphically represented in Figure 11(i).

4.4. Efficiency

The proposed 37-level MLI optimizes a number of crucial features that impact MLI efficiency, such as switching losses, conduction losses, THD, and component count. As compared to other topologies in Table 10, the suggested MLI outperforms several existing designs, such as the topology in [19, 21, 25, 32, 34] with an efficiency of 97.01%. Although certain additional designs, including [29] (97.2%) and [33] (97.28%), provide similar efficiency, they do so with either a higher component count or increased THD. By lowering THD to just 1.09%, decreasing switching losses, and maintaining high efficiency with fewer components per level, the suggested MLI achieves an ideal balance. As seen in Table 9, where the losses are low even under varied load situations, this efficiency is further enhanced by decreased conduction and switching losses during power conversion. The efficiency of the proposed MLI is compared to different topologies in Figure 13, indicating its excellent balance between high efficiency, minimal THD, and optimal component utilization. Thus, the proposed MLI achieves improved utilization of energy, which increases its reliability and cost-effectiveness.

Thus, from the above mentioned comparisons, it can be said that the proposed structure generates 37 levels of output voltage by using a lower number of components per level with lower harmonic contents in the output of only 1.09% THD, reducing switching losses during power conversion, and the switches experience reduced voltage stress by better utilizing the DC voltage source. These features help to reduce the cost of the inverter and thus contribute to better efficiency of the MLI, which are the prominent benefits of the proposed MLI. So, in many applications including renewable energy generation systems, EV drives, and control of electric machines, the proposed MLI can be a replacement for conventional MLIs.

5. Application

The proposed asymmetrical MLI is particularly well-suited for applications in renewable energy systems and EVs. Renewable energy sources, such as solar panels and wind turbines, frequently provide DC voltage that fluctuates according to the atmosphere. This variable DC voltage may be converted at different voltage levels by MLIs into high-quality AC voltage. Since various voltage levels may be needed for transmission or distribution, this flexibility is essential for the efficient integration of renewable energy sources into the grid. Besides this, MLIs can operate at higher voltages. As a result, the system’s current flow is decreased, which lowers resistive losses (I²R losses) and increases efficiency. In addition, MLIs provide a number of benefits that make them suitable for EVs. Electrical components in EVs operate more smoothly because MLI reduces electromagnetic interference. MLIs’ compact scalable structural design not only reduces both weight and space but also allows for the integration of EVs with different power ratings and voltage requirements, which are important factors in the efficiency and performance of EVs. So, the proposed MLIs’ features, which include greater voltage capabilities, enhanced efficiency, less harmonics, scalability, and dependability, make it an excellent choice for renewable energy systems and EVs.

6. Conclusion

A novel asymmetrical MLI structure has been designed in this paper which utilizes less components/levels to produce 37-level output voltage. The distribution of the stresses on the switches of the proposed inverter is visualized in detail which shows that only 7.69% of switches experience maximum stress which results in the use of lower high-rated devices and thus the cost of the components of the inverter circuit gets reduced. A comparison is made to evaluate the performance of the proposed MLI with some current topologies on the basis of a number of components per voltage level, THD, TSV, cost factor per level, and efficiency. Comparison results show that the proposed structure generates 37 levels of output voltage using fewer components per level, which is significantly lower than that of conventional designs, ensuring less power losses. In addition, the reduction in component count minimizes design complexity and overall cost. The proposed MLI has less TSV (3.03 pu) and the cost factor is less as well which is 0.85 for α = 0.5 and 0.93 for α = 1.5 in comparison to other current topologies; thus, it can be said that the proposed structure is cost-effective. The MLI has been evaluated in dynamically loaded conditions and it is found to be stable overall. The half-height modulation technique is used for calculating the switching angles by which higher quality output waveform is achieved with a THD of 1.09%, which is much less compared to current topologies. These factors contribute to the MLI’s high system efficiency of 97.01%, which is one of the key benefits of the proposed design. Design and simulation of the proposed 37-level MLI have been performed in MATLAB/Simulink. In order to achieve better performance in the future, future research may involve developing an improved version of the proposed structure with fewer switches, lower THD, and less switch voltage stress with a higher level of voltage at the output. For EVs and renewable energy systems, the proposed MLI is excellently fitted.

Conflicts of Interest

The authors declare no conflicts of interest.

Funding

This research received no external funding.

Open Research

Data Availability Statement

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Design and Performance Analysis of a Novel Asymmetrical Multilevel Inverter Structure With Reduced Components Using the Half-Height Modulation Technique

Abstract

1. Introduction

2. Proposed Inverter Circuit Configuration

2.1. Switching States of Operation of the Proposed Topology