Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology
This article is part of Special Issue:
Wu-Te Weng,
Yao-Jen Lee,
Horng-Chih Lin,
Tiao-Yuan Huang,
Corresponding Author
Wu-Te Weng
Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan nctu.edu.tw
Search for more papers by this authorYao-Jen Lee
National Nano Device Laboratories, Science-Based Industrial Park, 26 Prosperity Road 1, Hsinchu 30078, Taiwan ndl.org.tw
Search for more papers by this authorHorng-Chih Lin
Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan nctu.edu.tw
National Nano Device Laboratories, Science-Based Industrial Park, 26 Prosperity Road 1, Hsinchu 30078, Taiwan ndl.org.tw
Search for more papers by this authorTiao-Yuan Huang
Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan nctu.edu.tw
Search for more papers by this authorWu-Te Weng,
Yao-Jen Lee,
Horng-Chih Lin,
Tiao-Yuan Huang,
Corresponding Author
Wu-Te Weng
Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan nctu.edu.tw
Search for more papers by this authorYao-Jen Lee
National Nano Device Laboratories, Science-Based Industrial Park, 26 Prosperity Road 1, Hsinchu 30078, Taiwan ndl.org.tw
Search for more papers by this authorHorng-Chih Lin
Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan nctu.edu.tw
National Nano Device Laboratories, Science-Based Industrial Park, 26 Prosperity Road 1, Hsinchu 30078, Taiwan ndl.org.tw
Search for more papers by this authorTiao-Yuan Huang
Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan nctu.edu.tw
Search for more papers by this authorAcademic Editor: Paul K. Chu
Abstract
This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.
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