Volume 14, Issue 4 679267 pp. 315-327
Article
Open Access

A Fast ALU Design in CMOS for Low Voltage Operation

A. Srivastava

Corresponding Author

A. Srivastava

Department of Electrical and Computer Engineering Louisiana State University Baton Rouge, LA 70803-5901, USA , lsu.edu

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D. Govindarajan

D. Govindarajan

Department of Electrical and Computer Engineering Louisiana State University Baton Rouge, LA 70803-5901, USA , lsu.edu

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First published: 25 April 2001
Citations: 17

Abstract

A high-speed 4-bit ALU has been designed for 1 V operation to demonstrate the usefulness of the back-gate forward substrate bias (BGFSB) method in 1.2 μm N-well CMOS technology. The 4-bit ALU employs a ripple carry adder and is capable of performing eight operations - four arithmetic and four logical operations. The BGFSB voltage has been limited to |0.4| V. Delay time measurements are taken for all operations from the SPICE simulations with and without the back-gate forward substrate bias. A speed advantage of a factor of about 2–2.5 is obtained with BGFSB over the conventional design.

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