A wideband code-division multiple access (WCDMA) CMOS power amplifier with a mixed bias-mode scheme has been developed to meet high linearity and low-quiescent current requirements at the same time. The power stage of the two-stage power amplifier consists in three identical differential pairs that are selectively biased with a fixed bias mode or an adaptive bias mode. Each output power of three differential pairs is combined with an on-chip transformer to achieve output power requirement. The developed power amplifier shows 25.7% of power-stage drain efficiency at 27 dBm of output power with −33 dBc ACLR at 5 MHz offset in 1.95 GHz. The quiescent current of the mixed bias-mode power stage was 81 mA, whereas, it is 212 mA with the fixed bias mode. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2547–2552, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26367

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A mixed bias-mode power amplifier for WCDMA applications

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A mixed bias-mode power amplifier for WCDMA applications

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