Volume 30, Issue 3-4 e2186
RESEARCH ARTICLE

Effect of gate-length downscaling on the analog/RF and linearity performance of InAs-based nanowire tunnel FET

Biswajit Baral

Biswajit Baral

ECE Department, Silicon Institute of Technology, Bhubaneswar, Odisha, India

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Sudhansu Mohan Biswal

Sudhansu Mohan Biswal

ECE Department, Silicon Institute of Technology, Bhubaneswar, Odisha, India

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Debashis De

Debashis De

CSE Department, West Bengal University of Technology, Kolkata, West Bengal, India

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Angsuman Sarkar

Corresponding Author

Angsuman Sarkar

ECE Department, Kalyani Government Engineering College, Kolkata, West Bengal, India

Correspondence to: Angsuman Sarkar, ECE Department, Kalyani Government Engineering College, Kolkata, West Bengal, India.

E-mail: [email protected]

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First published: 15 August 2016
Citations: 12

Summary

In this paper, the analog/radio frequency (RF) and linearity performance of an InAs-based nanowire (NW) tunnel field-effect transistor (TFET) is studied and compared with InAs-based NW MSFET of identical dimension. InAs-based NW TFETs shows a great promise for high performance digital application because of its superior subthreshold behavior. Different analog/RF and linearity key figure-of-merits like cut-off frequency (ft) and 1-dB compression point are extracted and the effect of gate length down scaling on those parameters has been studied. The results reveal that down scaled InAs-based NW TFET shows a significant improvement in its RF and linearity performance. However, this advantage diminishes in terms of poor analog performance with gate-length downscaling. This clearly indicates the necessity of a trade-off between analog and RF performance. Moreover, an in-depth comparison between InAs-based NW TFET and conventional MOSFET has also been provided in order to demonstrate the superiority of InAs-based NW TFET to become a competitive contender by replacing conventional MOSFET for Analog/Mixed signal System-on-Chip (SOC) applications. Copyright © 2016 John Wiley & Sons, Ltd.

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