Engineering Reports
Volume 7, Issue 3 e70015
RESEARCH ARTICLE
Open Access

A New Transformer-Less Buck-Boost Converter With Reliability Assessment Using the Improved Markov Model

Ifham H. Malick, 

Ifham H. Malick

Department of Electrical Engineering, Zakir Husain College of Engineering and Technology (ZHCET), Aligarh Muslim University (AMU), Aligarh, India

Contribution: Methodology, ​Investigation, Formal analysis, Conceptualization, Writing - original draft, Software, Data curation, Visualization

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Mohammad Zaid, 

Mohammad Zaid

Department of Electrical Engineering, Zakir Husain College of Engineering and Technology (ZHCET), Aligarh Muslim University (AMU), Aligarh, India

Contribution: Conceptualization, Methodology, Supervision, Writing - review & editing, Software, Project administration, Data curation, Visualization, Resources

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Javed Ahmad, 

Javed Ahmad

Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan

Contribution: Validation, Writing - review & editing, Resources

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Chang-Hua Lin, 

Chang-Hua Lin

Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan

Contribution: Writing - review & editing

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Marwan Ahmed Abdullah Alasali, 

Corresponding Author

Marwan Ahmed Abdullah Alasali

Department of Mechatronics Engineering, Aljanad University for Science and Technology, Taizz, Yemen

Correspondence:

Marwan Ahmed Abdullah Alasali ([email protected])

Contribution: Funding acquisition

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First published: 03 March 2025
https://doi.org/10.1002/eng2.70015
Citations: 1

Funding: The authors received no specific funding for this work.

ABSTRACT

This work proposes a new continuous input current cubic gain buck-boost converter with a simple structure and reduced components. The converter has minimal components consisting of a twin-switch configuration with a broad range of duty-cycle operations. The converter attains unity gain at 24.51% duty cycle and can perform under both the continuous and discontinuous modes of conduction. Adding to the fundamental analysis of the converter, a study to examine the converter's volumetric distribution and cost factor calculation is also discussed. The averaged small-signal model of the converter is formulated to assess the transfer function and the stability of the converter during its operation. The converter's reliability is also determined to assess its performance using the improved Markov model. The discussion of the variation of the reliability and the MTTF with parameters like the duty cycle of the active switch, input voltage, and output power is also highlighted in the paper. The converter performs at an efficiency of 95.20% while it delivers 100 W output power, making it feasible for low- to medium-power applications. The converter's 200 W hardware prototype is presented, followed by a discussion of the corresponding results. Furthermore, the dynamic state survey of the converter is also presented, where step changes in input voltage, load, and duty cycle are being considered.

1 Introduction

The rapid fall in the reserves of conventional energy fuel sources and the steep rise in the power demands require clean, cheap, and abundant alternative fuels like solar PV, wind energy, and fuel cells. However, this generated low-voltage power needs to be stepped up to the grid operating levels using DC-DC converters, which act as an interface [1-3]. In response to this global push toward sustainable energy, buck-boost converters have found expanded operation in renewable energy systems. The literature encompasses numerous new and modified buck-boost converters trying to prevail over the constraints of the traditional buck-boost converter (TBBC), SEPI, ćuk, and zeta converters. The literature yields multiple resonant, hybrid-type, isolated, and nonisolated converters with advantages and disadvantages as per their efficacy [2, 4, 5].

The isolated converters [6-9] preferred for their high-power applications help improve the system's reliability and efficiency [1, 2] as the delicate elements are cocooned from the input surges. For low and medium power applications, isolated converters suffer from issues like leakage inducatance, increased cost, and weight due to the presence of a transformer. Therefore, low- to medium-power renewable applications require light and efficient nonisolated converters. The Z-source converters [9, 10] have diverse uses as they are packed with easy and straightforward component designs due to their symmetrical structure. The switching transients in these converters often cause severe stress across the active elements due to sudden transitions between conducting and nonconducting states. Several implementations of zero-voltage-switching and zero-current-switching converters [11, 12] aid in dealing with the setback. However, their load and resonant frequency-dependent characteristics restrict their usage. The converters [13-19] and the proposed converter are used in various duty-cycle operations with lower weight and higher efficiency in medium-power applications [20].

Apart from these issues, the converters are vulnerable to various thermoelectrical stresses [21]. These stresses leave a catastrophic residue in deteriorating and trimming the device's useful life by escalating the failure probability, thereby leading to an immature replacement of the converter component. The literature provides different methods for the estimation of reliability. However, the bathtub model [21, 22] in Figure 1 is adequate for computing the failure rates for the power electronic devices. Three intermittent zones comprise the bathtub curve: infant mortality, constant failure rate, and wear-out period, which give an overview of the component's trajectory over time. The device enters its wear-out phase after a sure useful life, during which it is subjected to a variety of electrical and thermal stresses [22]. A thorough reliability investigation on a range of traditional isolated converters is conducted in [21], providing a detailed understanding of the converters' long-term performance and dependability. The authors in [22, 23] claim a severe effect on reliability while the converter operates on extended duty ratios.

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FIGURE 1
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Various Zones in the Bathtub model [20].

The published literature composes sufficient buck-boost, high-gain boost, multiphase, and multilevel converters. On the contrary, they lack the proper reliability analysis, and hence, they fail to deliver an idea about the converter's operational characteristics and working stability over time [24, 25]. A converter will inevitably operate for a more extended period with minimal mean time to failure (MTTF) despite its high efficiency, constant input current, and low voltage and current stresses across the components. Thus, this article implements a new nonisolated cubic gain buck-boost converter with an appropriate reliability study.

The advantages of the presented converter topology are listed below:
  • The converter attains the unity gain at 24.51% duty cycle and is six times the gain compared to conventional buck-boost or SEPIC converter at 50% duty ratio. The converter operates in the buck region till 24.51% duty ratio and performs low-power operations effectively. The sooner the converter transitions to boost operation mode, the more the converter can operate at high-power operation as discussed ahead [21, 22].
  • The proposed converter operates at continuous input and output current, which results in higher efficiency and curtails the ripples of the input current [26, 27]. The continuity of input current allows solar PV to be easily interfaced as input. Furthermore, it also results in reduced EMI, smoother operation, and improved longevity of components.
  • The proposed nonisolated converter is free from transformers, coupled inductors, or transformers. Hence, no problem related to leakage inductance arises, making the converter less bulky and more reliable [24, 25].
  • The converter employs a twin-switch with a single-pulse-fed configuration, which grants easy switching control and helps to increase the system's reliability as partial power can be fed to the load if any active component experiences a fault.
  • The presented new buck-boost converter functions in the partial power state, even when multiple semiconductors experience an OC or SC fault as provided in [28, 29]. The work also thoroughly examines the reliability of converters with different failures.

The paper follows the following structure: Section 1 provides the introduction, and Section 2 discusses the implementation and converter's configuration under steady-state operation. Section 3 imparts the averaged small-signal modeling followed by the transfer function formulation of the converter. Section 4 enlists the comparison of the converter with various similar converters available in the literature and enlightens the advantages and superiority of the proposed converter, taking in different parametrical aspects. Section 5 lays out the reliability analysis of the converter using the improved Markov model to judge the converter's performance over time and grasp a typical operating time cycle of the converter. Section 6 furnishes the experimental validation of the converter by proposing a 50 W/200 W hardware prototype for various duty ratios, and Section 7 follows the dynamic state analysis of the converter as it experiences an instantaneous change in input voltage, load, and duty cycle. The paper finally concludes in Section 7.

2 Steady-State Operation of the Proposed Buck-Boost Converter Topology

The topology of the proposed cubic gain buck-boost converter, shown in Figure 2, consists of a voltage source V in $$ \left({V}_{in}\right) $$ , two active switches S 1 − S 2 $$ \left({S}_1-{S}_2\right) $$ , three inductors L 1 − L 3 $$ \left({L}_1-{L}_3\right) $$ , three capacitors C O − C 2 $$ \left({C}_O-{C}_2\right) $$ , four diodes D O − D 3 $$ \left({D}_O-{D}_3\right) $$ , and a load R O $$ \left({R}_O\right) $$ . The converter's operation is discussed using suitable CCM and DCM modes' equations.

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FIGURE 2
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Proposed cubic gain buck-boost converter.

2.1 The Operating Principle of the Converter in CCM

  1. Mode 1 (Both switches ON): Only the diode D 3 $$ {D}_3 $$ conducts when both the switches are given a high pulse signal. The inductors L 1 $$ {L}_1 $$ get charged directly through the supply voltage V in $$ {V}_{in} $$ . The capacitors C 1 $$ {C}_1 $$ and C 2 $$ {C}_2 $$ charge the inductors L 2 $$ {L}_2 $$ and L 3 $$ {L}_3 $$ . The load R o $$ {R}_o $$ is directly fed through the capacitor C O $$ {C}_O $$ shown in Figure 3a. The voltage across and current through passive elements of the converter in mode one are given as,
    V L 1 ON = V in V L 2 ON = V C 1 + V C 2 V L 3 ON = V C 1 V CO = V O , $$ \left\{\begin{array}{l}{V}_{L_{1_{ON}}}={V}_{in}\\ {}{V}_{L_{2_{ON}}}={V}_{C1}+{V}_{C2}\\ {}{V}_{L_{3_{ON}}}={V}_{C1}\\ {}{V}_{CO}={V}_O\end{array}\right., $$ (1)
    I C 1 ON = I L 2 + I L 3 I C 2 ON = I L 2 I C O ON = I O . $$ \left\{\begin{array}{l}{I}_{C_{1_{ON}}}={I}_{L2}+{I}_{L3}\\ {}{I}_{C_{2_{ON}}}={I}_{L2}\\ {}{I}_{C_{O_{ON}}}={I}_O\end{array}\right.. $$ (2)
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FIGURE 3
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(a) Proposed buck-boost converter in ON-state mode. (b) Proposed buck-boost converter in OFF-state mode.
  1. Mode 2 (Both switches OFF): The diodes D O $$ {D}_O $$ , D 1 $$ {D}_1 $$ , and D 2 $$ {D}_2 $$ conduct when the switches are in the OFF state. The capacitor C 1 $$ {C}_1 $$ is charged from the source while the inductors L 2 $$ {L}_2 $$ and L 3 $$ {L}_3 $$ feed the load, as shown in Figure 3b. The voltage across and current through passive elements of the converter in mode two are given as,
    V L 1 OFF = V in − V C 1 V L 2 OFF = V C 2 − V O V L 3 OFF = − V C 2 , $$ \left\{\begin{array}{l}{V}_{L_{1_{OFF}}}={V}_{in}-{V}_{C1}\\ {}{V}_{L_{2_{OFF}}}={V}_{C2}-{V}_O\\ {}{V}_{L_{3_{OFF}}}=-{V}_{C2}\end{array}\right., $$ (3)
    I C 1 OFF = − I L 1 I C 2 OFF = I L 2 − I L 3 I C O OFF = I O − I L 2 . $$ \left\{\begin{array}{l}{I}_{C_{1_{OFF}}}=-{I}_{L1}\\ {}{I}_{C_{2_{OFF}}}={I}_{L2}-{I}_{L3}\\ {}{I}_{C_{O_{OFF}}}={I}_O-{I}_{L2}\end{array}\right.. $$ (4)
The voltage gain of the proposed topology for CCM operation is calculated by applying the volt-sec balance equation as given in (5) for every “ith” inductor in the converter to obtain the relations given in (6),
1 T ∫ 0 DT V L i ON dt + ∫ DT T V L i OFF dt = 0 , $$ \frac{1}{T}\left(\int_0^{DT}{V}_{L{i}_{ON}}\ dt+\int_{DT}^T{V}_{L{i}_{OFF}}\ dt\right)=0, $$ (5)
V C 1 = V in ( 1 − D ) V C 2 = ( 1 − D ) V O − DV C 1 V C 2 = DV C 1 ( 1 − D ) . $$ \left\{\begin{array}{l}{V}_{C1}=\frac{V_{in}\ }{\left(1-D\right)}\\ {}{V}_{C2}=\left(1-D\right){V}_O-{DV}_{C1}\\ {}{V}_{C2}=\frac{DV_{C1}}{\left(1-D\right)}\end{array}\right.. $$ (6)
Rearranging the expressions in Equation (6), we can obtain the CCM voltage gain as,
M CCM = V 0 V in = D ( 2 − D ) ( 1 − D ) 3 , $$ {M}_{CCM}=\frac{V_0}{V_{in}}=\frac{D\left(2-D\right)}{{\left(1-D\right)}^3}, $$ (7)
where “D” represents the typical duty cycle for the switches.

2.2 The Voltage Across and Current Through the Various Elements

The average voltage across capacitors and the peak voltage stress across the switches (obtained by applying KVL), as shown in Figures 4 and 5, are given as,
V C 1 = V S 1 = V D 1 = V in ( 1 − D ) V C 2 = DV in ( 1 − D ) 2 V CO = D ( 2 − D ) V in ( 1 − D ) 3 V S 2 = V DO = V in ( 1 − D ) 3 V D 2 = V in ( 1 − D ) 2 V D 3 = DV in ( 1 − D ) 3 . $$ \left\{\begin{array}{l}{V}_{C1}={V}_{S1}={V}_{D1}=\frac{V_{in}}{\left(1-D\right)}\\ {}{V}_{C2}=\frac{DV_{in}}{{\left(1-D\right)}^2}\\ {}{V}_{CO}=\frac{D\left(2-D\right){V}_{in}}{{\left(1-D\right)}^3}\\ {}\begin{array}{c}{V}_{S2}=\end{array}{V}_{DO}=\frac{V_{in}}{{\left(1-D\right)}^3}\\ {}{V}_{D2}=\frac{V_{in}}{{\left(1-D\right)}^2}\\ {}{V}_{D3}=\frac{DV_{in}}{{\left(1-D\right)}^3}\end{array}\right.. $$ (8)
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FIGURE 4
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Typical voltage and current waveforms in CCM operation.
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FIGURE 5
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(a) Voltage stress across switches in CCM operation. (b) Voltage stress across diodes in CCM operation.
The average currents through the switches and inductors can be determined as,
1 T ∫ 0 DT I C i ON dt + ∫ DT T I C i OFF dt = 0 . $$ \frac{1}{T}\left(\int_0^{DT}{I}_{C{i}_{ON}}\ dt+\int_{DT}^T{I}_{C{i}_{OFF}}\ dt\right)=0. $$ (9)
The average current through the inductor and peak current through the semiconductor components, as shown in Figure 4, are given as,
I L 1 = I S 1 peak = I D 1 peak = I in I L 2 = ( 1 − D ) 2 I in D ( 2 − D ) I L 3 = I D 2 peak = I D 3 peak = ( 1 − D ) I in D ( 2 − D ) I S 2 peak = DI in ( 1 − D ) I DO peak = ( 1 − D ) 3 I in D ( 2 − D ) . $$ \left\{\begin{array}{l}{I}_{L1}={I}_{S_{1_{peak}}}={I}_{D{1}_{peak}}={I}_{in}\\ {}{I}_{L2}=\frac{{\left(1-D\right)}^2\ {I}_{in}}{D\left(2-D\right)}\\ {}{I}_{L3}={I}_{D{2}_{peak}}={I}_{D{3}_{peak}}=\frac{\left(1-D\right){I}_{in}}{D\left(2-D\right)}\\ {}{I}_{S_{2_{peak}}}=\frac{DI_{in}}{\left(1-D\right)}\\ {}{I}_{DO_{peak}}=\frac{{\left(1-D\right)}^3\ {I}_{in}}{D\left(2-D\right)}\end{array}\right.. $$ (10)

2.3 Design of Passive Elements

The ripple current and the corresponding critical values of the inductors, peak-to-peak capacitor ripples, for continuous current can be calculated as,
L i cri = V L i ON Δ i L i DT C i cri = I C i ON Δ v C i DT , $$ \left\{\begin{array}{l}{L}_{i_{cri}}=\frac{V_{L_{i_{ON}}}\ }{\Delta {i}_{L_i}} DT\\ {}{C}_{i_{cri}}=\frac{I_{C_{i_{ON}}}\ }{\Delta {v}_{C_i}} DT\end{array}\right., $$ (11)
L 1 Cri = ( 1 − D ) 3 V O ( 2 − D ) Δ i L 1 f s L 2 Cri = ( 1 − D ) V O ( 2 − D ) Δ i L 2 f s L 3 Cri = ( 1 − D ) 2 V O ( 2 − D ) Δ i L 3 f s C 1 = V 0 ( 2 − D ) R O Δ V C 1 f s C 2 = D V 0 ( 1 − D ) R O Δ V C 2 f s C O = D V 0 R O Δ V CO f s . $$ \left\{\begin{array}{l}{L}_{1_{Cri}}=\frac{{\left(1-D\right)}^3\ {V}_O}{\left(2-D\right)\Delta {i}_{L1}{f}_s}\\ {}{L}_{2_{Cri}}=\frac{\left(1-D\right){V}_O}{\left(2-D\right)\Delta {i}_{L2}{f}_s}\\ {}{L}_{3_{Cri}}=\frac{{\left(1-D\right)}^2{V}_O}{\left(2-D\right)\Delta {i}_{L3}{f}_s}\\ {}{C}_1=\frac{V_0}{\left(2-\mathrm{D}\right){R}_O\Delta {V}_{C1}{f}_s}\\ {}{C}_2=\frac{D\ {V}_0}{\left(1-\mathrm{D}\right){R}_O\Delta {V}_{C2}{f}_s}\\ {}{C}_O=\frac{D\ {V}_0}{R_O\Delta {V}_{CO}{f}_s}\end{array}\right.. $$ (12)

The values of the inductors and capacitors can be estimated by assuming the per-unit current and voltage ripples between 20% and 30% and 3% and 4%, respectively.

2.4 The Boundary (BCM) and Discontinuous (DCM) Conduction Mode Working

In BCM, depicted in Figure 6, the inductor L 2 $$ {L}_2 $$ or L 3 $$ {L}_3 $$ or both conduct in critical conduction mode. The normalized inductor time constant K BCM $$ \left({K}_{BCM}\right) $$ , for inductors L2 and L3 is shown in Figure 6.

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FIGURE 6
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Boundary normalized inductor time constant versus duty cycle (D).
The inductor operating under BCM will have a zero value for the minimum inductor current, which would result in the following equations:
Δ I L i = I L i max − I L i min I L i = I L i max − I L i min 2 I L i = Δ i L i 2 . $$ \left\{\begin{array}{l}\Delta {I}_{L_i}={I}_{L_{imax}}-{I}_{L_{imin}}\\ {}{I}_{L_i}=\frac{I_{L_{imax}}-{I}_{L_{imin}}}{2}\\ {}{I}_{L_i}=\frac{\Delta {i}_{L_i}}{2}\end{array}\right.. $$ (13)
Using the inductor voltage relations and the above derived equations, we can obtain the normalized inductor time constants as,
L i R O T = D V L i ON 2 I L i R O , $$ \frac{L_i}{R_OT}=\frac{D\;{V}_{L_{i_{ON}}}}{2\;{I}_{L_i}{R}_O}, $$
where V L i ON $$ {V}_{L{i}_{ON}} $$ is the function of the output voltage, which can be represented in terms of the load resistance using Ohm's law.
K L 2 = L 2 R O T = ( 1 − D ) 2 2 ( 2 − D ) K L 3 = L 3 R O T = D ( 1 − D ) 3 2 ( 2 − D ) . $$ \left\{\begin{array}{l}{K}_{L_2}=\frac{L_2}{R_OT}=\frac{{\left(1-D\right)}^2}{2\left(2-D\right)}\\ {}{K}_{L_3}=\frac{L_3}{R_OT}=\frac{D{\left(1-D\right)}^3}{2\left(2-D\right)}\end{array}\right.. $$ (14)
The inductor L 1 $$ {L}_1 $$ ; however, it can be inhibited from the DCM operation as it will result in a discontinuous source current, which is undesirable for renewable energy applications. The proposed converter can also operate in DCM. The converter can achieve DCM operation in two ways, that is, when discontinuous current flows through inductor L2 or L3. The first two modes of operation are the same for both conditions and are similar to the regular CCM operation. However, the third mode depends on the inductor, which experiences a discontinuous current.
  1. Mode 1: Here, the switches are ON for a time DT $$ DT $$ , similar to the CCM operation where only the diode D 3 $$ {D}_3 $$ conducts for a duration of DT $$ DT $$ , as shown in Figure 7.
  2. Mode 2: Here, the switches are OFF for the duration ( β − D ) T $$ \left(\beta -D\right)T $$ , and the inductors start discharging as diodes D O $$ {D}_O $$ , D 1 $$ {D}_1 $$ , and D 2 $$ {D}_2 $$ conduct.
  3. Mode 3(a) (DCM operation in L 2 $$ {\mathbf{L}}_{\mathbf{2}} $$ ): In this mode, none of the switches conduct with the diode DO ceasing to operate, as shown in Figure 8a. The diodes D 1 $$ {D}_1 $$ and D 2 $$ {D}_2 $$ conduct, which eventually results in the continuous current operation of inductors L 1 $$ {L}_1 $$ and L 3 $$ {L}_3 $$ while the current through the inductor L 2 $$ {L}_2 $$ becomes discontinuous. The resistor is fed solely through the energy stored in the output capacitor C O $$ {C}_O $$ . The converter operates for a duration of ( 1 – β ) T $$ \left(1\hbox{--} \beta \right)\kern0.6em T $$ , as depicted in Figure 8a. The voltage across the inductors during this mode is given as,
    V L 1 = V in − V C 1 V L 2 = 0 V L 3 = − V C 2 . $$ \left\{\begin{array}{l}{V}_{L1}={V}_{in}-{V}_{C1}\\ {}{V}_{L2}=0\\ {}{V}_{L3}=-{V}_{C2}\end{array}\right.. $$ (15)
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FIGURE 7
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Various voltages and currents during the DCM operation.
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FIGURE 8
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(a) Proposed topology operation in DCM mode 3(a). (b) Proposed topology operation in DCM mode 3(b).
  1. Mode 3(b) (DCM operation in L 3 $$ {\mathbf{L}}_{\mathbf{3}} $$ ): In this mode, as in the previous case, none of the switches conduct Figure 8b. The diodes D O $$ {D}_O $$ and D 1 $$ {D}_1 $$ conduct, which eventually results in the continuous current operation of inductors L 1 $$ {L}_1 $$ and L 2 $$ {L}_2 $$ while the current through the inductor L 3 $$ {L}_3 $$ becomes discontinuous in this case. The resistor is fed through the energy stored in the inductor L 2 $$ {L}_2 $$ for this duration. The converter operates for ( 1 – β ) T $$ \left(1\hbox{--} \beta \right)\kern0.5em T $$ , as depicted in Figure 8b. The voltage across various inductors in this mode is given as,
    V L 1 = V in − V C 1 V L 2 = V C 2 − V O V L 3 = 0 . $$ \left\{\begin{array}{l}{V}_{L1}={V}_{in}-{V}_{C1}\\ {}{V}_{L2}={V}_{C2}-{V}_O\\ {}{V}_{L3}=0\end{array}\right.. $$ (16)
The same DCM gain of the converter for each operation remains the same and is given as,
M DCM = V 0 V in = D ( 1 + β − D ) ( β − D ) ( 1 − D ) 2 . $$ {M}_{DCM}=\frac{V_0}{V_{in}}=\frac{D\left(1+\beta -D\right)}{\left(\upbeta -D\right){\left(1-D\right)}^2}. $$ (17)

2.5 Volumetric Analysis of Passive Components Utilized in the Proposed Converter

The volume of the passive components can be analyzed by computing the energy storage requirement of the element during the converter's operation. To assess the volume, we first evaluate the power which is processed by the energy-storing elements and then move on to determine the energy stored by the passive elements [26]. The higher switching frequency allows the elements to store lower energy; hence, the converter's volume and size are reduced. However, as the frequency is increased, the reliability and, hence, the MTTF reduce drastically [23]. The total passive component volume can be figured out by assessing the energy density of the element from the suitable datasheet provided by the manufacturer.

The instantaneous power flowing through the ith passive energy-storing element can be given as,
P i = 1 T ∫ 0 T I i ( t ) × V i ( t ) dt . $$ {P}_i=\frac{1}{T}{\int}_0^T\left|{I}_i(t)\times {V}_i(t)\right| dt. $$ (18)
As we know, the average power stored in the element is zero over a switching duration, and we can now establish a simplified relation as,
P i = 1 T ∫ 0 DT I i ( t ) × V i ( t ) dt + ∫ DT T I i ( t ) × V i ( t ) dt . $$ {P}_i=\frac{1}{T}\left[\left({\int}_0^{DT}\left|{I}_i(t)\times {V}_i(t)\right| dt\right)+\left({\int}_{DT}^T\left|{I}_i(t)\times {V}_i(t)\right| dt\right)\right]. $$ (19)
The magnitudes of the power stored and released during each switching cycle break even. Hence,
P i = 2 T ∫ 0 DT I i ( t ) × V i ( t ) dt . $$ {P}_i=\frac{2}{T}{\int}_0^{DT}\left|{I}_i(t)\times {V}_i(t)\right| dt. $$ (20)
Following the Equation (19), the power across the various elements can be listed as,
P L 1 = 2 DP O P L 2 = 2 2 − D P O P L 3 = 2 2 − D P O P C 1 = 2 P O P C 2 = 2 D 2 − D P O P C 3 = 2 DP O . $$ \left\{\begin{array}{l}{P}_{L_1}=2{DP}_O\\ {}{P}_{L_2}=\frac{2}{2-D}{P}_O\\ {}{P}_{L_3}=\frac{2}{2-D}{P}_O\\ {}{P}_{C_1}=2{P}_O\\ {}{P}_{C_2}=\frac{2D}{2-D}{P}_O\\ {}{P}_{C_3}=2{DP}_O\end{array}\right.. $$ (21)
The energy processed by the element i will be a function of the average output power flowing through the elements and the switching frequency of the switch (fsw),
E i = P i f sw . $$ {E}_i=\frac{P_i}{f_{sw}}. $$ (22)
Conversely, for jth capacitor and kth inductor, the energy stored will also be a function of the ripple voltage and ripple current, respectively,
E C j = 1 2 C j V C j + Δ V C j 2 2 − V C j − Δ V C j 2 2 = C j V C j Δ V C j E L k = 1 2 L k I L k + Δ I L k 2 2 − I L k − Δ I L k 2 2 = L k I L k Δ I L k , $$ \left\{\begin{array}{l}{E}_{C_j}=\frac{1}{2}{C}_j\left[{\left({V}_{C_j}+\frac{\varDelta {V}_{C_j}}{2}\right)}^2-{\left({V}_{C_j}-\frac{\varDelta {V}_{C_j}}{2}\right)}^2\right]={C}_j{V}_{C_j}\varDelta {V}_{C_j}\\ {}{E}_{L_k}=\frac{1}{2}{L}_k\left[{\left({I}_{L_k}+\frac{\varDelta {I}_{L_k}}{2}\right)}^2-{\left({I}_{L_k}-\frac{\varDelta {I}_{L_k}}{2}\right)}^2\right]={L}_k{I}_{L_k}\varDelta {I}_{L_k}\end{array}\right., $$ (23)
where E C j $$ {E}_{C_j} $$ and E L k $$ {E}_{L_k} $$ do the capacitor and inductor store the average energy, respectively.
The energy utilization factor ( μ ) $$ \left(\mu \right) $$ for the passive element is judged by co-relating the average energy stored to the maximum energy stored by the element,
μ C = E C j E C j max = 2 Δ V C j V C j 1 + Δ V C j 2 V C j 2 μ L = E L k E L k max = 2 Δ I L k I L k 1 + Δ I L k 2 I L k 2 . $$ \left\{\begin{array}{l}{\mu}_C=\frac{E_{C_j}}{{\left({E}_{C_j}\right)}_{max}}=\frac{2\frac{\varDelta {V}_{C_j}}{V_{C_j}}}{{\left(1+\frac{\varDelta {V}_{C_j}}{2{V}_{C_j}}\right)}^2}\\ {}{\mu}_L=\frac{E_{L_k}}{{\left({E}_{L_k}\right)}_{max}}=\frac{2\frac{\varDelta {I}_{L_k}}{I_{L_k}}}{{\left(1+\frac{\varDelta {I}_{L_k}}{2{I}_{L_k}}\right)}^2}\end{array}\right.. $$ (24)
To simplify the expression, we can opt binomial approximation,
μ C ≈ 2 Δ V C j V C j 1 + Δ V C j V C j μ L ≈ 2 Δ I L k I L k 1 + Δ I L k I L k . $$ \left\{\begin{array}{l}{\mu}_C\approx \frac{2\frac{\varDelta {V}_{C_j}}{V_{C_j}}}{1+\frac{\varDelta {V}_{C_j}}{V_{C_j}}}\\ {}{\mu}_L\approx \frac{2\frac{\varDelta {I}_{L_k}}{I_{L_k}}}{1+\frac{\varDelta {I}_{L_k}}{I_{L_k}}}\end{array}\right.. $$ (25)

The energy utilization factor assists in grasping the degree to which the element's energy-storing capacity is utilized. A higher value of the factor depicts a high utilization of the element's energy-storing property and signifies that a small-sized element can also be used for the same application.

The volume occupied by the ith element can be gained by its relation with the peak energy stored by the element E i max $$ \left({E}_{i_{max}}\right) $$ with its energy density ρ E i $$ \left({\rho}_{E_i}\right) $$ and energy density μ i $$ \left({\mu}_i\right) $$ as,
( Vol ) i = E i max ρ E i = P i ρ E i f sw μ i . $$ {(Vol)}_i=\frac{E_{i_{max}}}{\rho_{E_i}}=\frac{P_i}{\rho_{E_i}\ {f}_{sw}\ {\mu}_i}. $$ (26)
The total required volume of all the passive elements can be obtained by summation of all the volumes
( Vol ) total = 1 ρ E C f sw μ C ∑ j = 0 N C P C i + 1 ρ E L f sw μ L ∑ j = 0 N L P L i . $$ {(Vol)}_{total}=\frac{1}{\rho_{E_C}\ {f}_{sw}\ {\mu}_C}\sum \limits_{j=0}^{N_C}{P}_{C_i}+\frac{1}{\rho_{E_L}\ {f}_{sw}\ {\mu}_L}\sum \limits_{j=0}^{N_L}{P}_{L_i}. $$ (27)

2.6 Cost Factor Formulation of the Proposed Converter

The converter's cost factor (CF) can be used to assess the establishing cost associated with the converter while implementing it for practical applications. Hence, the CF is defined by analyzing the manufacturing cost of elements and the complexity of switch driver requirements as a function of the voltage gain offered by the converter.
CF = Total No . of components + No . of Switch drivers Voltage Gain M CCM . $$ CF=\frac{Total\ No. of\ components+ No. of\ Switch\ drivers}{Voltage\ Gain\ \left({M}_{CCM}\right)}. $$ (28)
The proposed converter consists of a total of 12 components. As both switches require the same gate pulse, a single switch driver can complete the job. The CF can hence be written as,
CF = 13 ( 1 − D ) 3 D ( 2 − D ) . $$ CF=\frac{13{\left(1-D\right)}^3}{D\left(2-D\right)}. $$ (29)

2.7 Efficiency and Power Loss Analysis of the Proposed Converter

The majority of the power losses in practical DC-DC converters include copper losses, switching losses, and ripple current/voltage losses. The copper losses are due to the parasitic resistance in inductors and active devices or ESR in capacitors. The copper losses across various elements used in the converter due to their parasitic resistance and cut-in voltages, which cause a hindrance to the converter achieving high efficiency, can be inferred from the relations in (30). The power loss for passive elements is evaluated by the heat loss across their parasitic resistance, whereas for the active elements, the switching loss for the switches and voltage drop across the diodes are also considered in addition to the heat losses. On the other hand, switching losses occur in active devices due to their constant high-frequency switching over time. This is why the converters are inhibited from high-frequency switching. The ripple losses arise due to the current pulses in inductor current and capacitor voltages, which tend to deviate from their ideal DC nature. The ripples in the inductor current and capacitor voltage increase the RMS current through the inductor and the voltage across the capacitor, leading to higher losses in these respective components. Due to these ripples, there are additional copper and core losses in the inductor while additional dielectric losses are associated with the capacitor.

The losses due to the parasitic resistances of the various passive and active devices used in the system are given as,
P L total = ∑ i = 0 N L I L rms i 2 r L i P C total = ∑ i = 0 N C I C rms i 2 r C i P S Cu = ∑ i = 0 N S I S rms i 2 r S i P D Cu = ∑ i = 0 N D I D rms i 2 r D i + I D avg i V D i , $$ \left\{\begin{array}{l}{P}_{L_{total}}=\sum \limits_{i=0}^{N_L}{I}_{L_{rms_i}}^2{r}_{L_i}\\ {}{P}_{C_{total}}=\sum \limits_{i=0}^{N_C}{I}_{C_{rms_i}}^2{r}_{C_i}\\ {}{P}_{S_{Cu}}=\sum \limits_{i=0}^{N_S}{I}_{S_{rms_i}}^2{r}_{S_i}\\ {}{P}_{D_{Cu}}=\sum \limits_{i=0}^{N_D}\left({I}_{D_{rms_i}}^2{r}_{D_i}+{I}_{D_{avg_i}}{V}_{D_i}\right)\end{array}\right., $$ (30)
P L total = D ( 2 − D ) ( 1 − D ) 3 2 r L 1 R O + 2 − 2 D + D 2 ( 1 − D ) 4 r L 2 R O P O P C total = 5 − 6 D − 2 D 2 ( 1 − D ) 4 r C R O P O P S Cu = D 2 − 6 D + 3 D 2 ( 1 − D ) 6 r S R O P O P D Cu = 2 + 7 D + 2 D 2 + 5 D 3 + D 4 ( 1 − D ) 5 r D R O P O , $$ \left\{\begin{array}{l}{P}_{L_{total}}=\left[{\left(\frac{D\left(2-D\right)}{{\left(1-D\right)}^3}\right)}^2\frac{r_{L_1}}{R_O}+\left(\frac{2-2D+{D}^2}{{\left(1-D\right)}^4}\right)\frac{r_{L_2}}{R_O}\right]{P}_O\\ {}{P}_{C_{total}}=\left(\frac{5-6D-2{D}^2}{{\left(1-D\right)}^4}\right)\frac{r_C}{R_O}{P}_O\\ {}{P}_{S_{Cu}}=\frac{D\left(2-6D+3{D}^2\right)}{{\left(1-D\right)}^6}\frac{r_S}{R_O}{P}_O\\ {}{P}_{D_{Cu}}=\frac{2+7D+2{D}^2+5{D}^3+{D}^4}{{\left(1-D\right)}^5}\frac{r_D}{R_O}{P}_O\end{array}\right., $$ (31)
where r L i $$ {r}_{L_i} $$ is the parasitic resistance of the “ith” inductor, r C i $$ {r}_{C_i} $$ is the ESR of the “ith” capacitor, r S i $$ {r}_{S_i} $$ represents the ON-state resistance of the “ith” switch, and r D i $$ {r}_{D_i} $$ is the ON-state resistance of the “ith” diode used in the converter topology.
The switching losses across the various elements of the converter are given as,
P S Sw = ∑ i = 0 N S I S avg i V S i × t r + t f 2 f s P D Sw = ∑ i = 0 N D Q rr i V r i 2 f s , $$ \left\{\begin{array}{l}{P}_{S_{Sw}}=\sum \limits_{i=0}^{N_S}\left({I}_{S_{avg_i}}{V}_{S_i}\right)\times \left(\frac{t_r+{t}_f}{2}\right){f}_s\\ {}{P}_{D_{Sw}}=\sum \limits_{i=0}^{N_D}\frac{Q_{rr_i}{V}_{r_i}}{2}{f}_s\end{array}\right., $$ (32)
where Q rr i $$ {Q}_{rr_i} $$ is the reverse recovery charge stored in the diode, and V rr i $$ {V}_{rr_i} $$ is the reverse recovery voltage of the diode during reversed biased condition.
The ripple losses across the various elements of the converter are given as,
P L rp = ∑ i = 0 N L I i ripple rms 2 r L i + K c i f s α B i peak β P C rp = ∑ i = 0 N C I ripple rms i 2 r C i + 2 π f s C i V i rms 2 tanδ . $$ \left\{\begin{array}{l}{P}_{L_{rp}}=\sum \limits_{i=0}^{N_L}\left({I}_{i_{ripple_{rms}}}^2{r}_{L_i}+{K}_{c_i}{f}_s^{\alpha }{B}_{i_{peak}}^{\beta}\right)\\ {}{P}_{C_{rp}}=\sum \limits_{i=0}^{N_C}\left({I}_{ripple_{rms_i}}^2{r}_{C_i}+2\pi {f}_s{C}_i\ {V}_{i_{rms}}^2\ tan\delta \right)\end{array}\right.. $$ (33)

In the above equations, K c i $$ {K}_{c_i} $$ , α $$ \alpha $$ , and β $$ \beta $$ are constants, B i peak $$ {B}_{i_{peak}} $$ is peak magnetic field, and tanδ $$ tan\delta $$ is the loss angle for the capacitor.

The summation of all the above losses will provide the total losses occurring across the various elements of the converter.

Using the loss relations obtained, the converter's efficiency can also be evaluated in terms of power loss and output power using the relations enlisted in [27].
η = 1 1 + P loss P O = 1 1 + P L total + P C total + P S total + P D total P O . $$ \eta =\frac{1}{1+\frac{P_{loss}}{P_O}}=\frac{1}{1+\frac{P_{L_{total}}+{P}_{C_{total}}+{P}_{S_{total}}+{P}_{D_{total}}}{P_O}}. $$ (34)

Figure 9 infers that the converter's efficiency increases as the input voltage increases. However, it gradually decreases as the output power increases. The converter operates at an efficiency of 93.0%, 94.2%, and 95.2% when the input voltage is 20, 30, and 40 V, respectively, as the converters operate at 100 W. The percentage contribution of various losses in the converter, as in Figure 10, infers that the inductors have contributed a maximum of 45% toward the overall losses. In contrast, capacitors contributed the least toward the total losses. The inductors and switches contribute 78% of the total losses, making using inductors and switches with low parasitic resistance essential. To minimize the losses in the converter diodes with lower on-state resistance and the least cut-in voltage, capacitors with lower equivalent series resistance (ESR) are chosen. Figure 11 depicts the decline in the voltage gain as the parasitic resistance of various components comes into the picture. The inductor's resistance significantly affects the converter's gain compared to the switch's on-state resistance.

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FIGURE 9
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Simulated efficiency versus output power characteristics of the converter.
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FIGURE 10
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Power Loss across various components.
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FIGURE 11
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Ideal Gain and its variation with nonidealitiex.

3 Small-Signal Modeling of the Converter

Small-signal modeling assesses the converter's transfer function and performance when operating in open-loop conditions. The state variables considered for the analysis are the currents through the inductors and voltages across the capacitors x = i L 1 i L 2 i L 3 v C 1 v C 2 v C O T $$ \left(x={\left[{i}_{L_1}\kern0.5em {i}_{L_2}\kern0.5em {i}_{L_3}\kern0.5em {v}_{C_1}\kern0.5em {v}_{C_2}\kern0.5em {v}_{C_O}\right]}^T\right) $$ . The input voltage and duty cycle are designated as “u,” whereas the output capacitor voltage is designated as “y.” Using space vector linearization, we get
x ˙ = Ax + Bu = Ax + B 1 d + B 2 v in y = Cx + Du . $$ \left\{\begin{array}{l}\dot{x}= Ax+ Bu= Ax+{B}_1d+{B}_2{v}_{in}\\ {}y= Cx+ Du\end{array}\right.. $$ (35)
The primary governing equations for the converter in the time domain and the corresponding signal modeling are represented as,
L 1 di L 1 dt = dv in + ( 1 − d ) v in − v C 1 L 2 di L 2 dt = d v C 1 + v C 2 + ( 1 − d ) v C 1 − v O L 3 di L 3 dt = dv C 1 + ( 1 − d ) − v C 2 C 1 dv C 1 dt = d i L 2 + i 3 + ( 1 − d ) − i L 1 C 2 dv C 2 dt = d i L 2 + ( 1 − d ) i L 2 − i 3 C O dv C O dt = d v C O R + ( 1 − d ) v C O R − I L 2 , $$ \left\{\begin{array}{l}{L}_1\frac{di_{L_1}}{dt}={dv}_{in}+\left(1-d\right)\left({v}_{in}-{v}_{C_1}\right)\\ {}{L}_2\frac{di_{L_2}}{dt}=d\left({v}_{C_1}+{v}_{C_2}\right)+\left(1-d\right)\left({v}_{C_1}-{v}_O\right)\\ {}{L}_3\frac{di_{L_3}}{dt}={dv}_{C_1}+\left(1-d\right)\left(-{v}_{C_2}\right)\\ {}{C}_1\frac{dv_{C_1}}{dt}=d\left({i}_{L_2}+{i}_3\right)+\left(1-d\right)\left(-{i}_{L_1}\right)\\ {}{C}_2\frac{dv_{C_2}}{dt}=d\left({i}_{L_2}\right)+\left(1-d\right)\left({i}_{L_2}-{i}_3\right)\\ {}{C}_O\frac{dv_{C_O}}{dt}=d\left(\frac{v_{C_O}}{R}\right)+\left(1-d\right)\left(\frac{v_{C_O}}{R}-{I}_{L_2}\right)\end{array}\right., $$ (36)
d = D + d ^ i L j = I L j + i L j ^ v C j = V C j + v C j ^ v in = V in + v in ^ . $$ \left\{\begin{array}{l}d=D+\hat{d}\\ {}{i}_{L_j}={I}_{L_j}+\hat{i_{L_j}}\\ {}{v}_{C_j}={V}_{C_j}+\hat{v_{C_j}}\\ {}{v}_{in}={V}_{in}+\hat{v_{in}}\end{array}\right.. $$ (37)
Solving the above equations, we get,
A = 0 0 0 − ( 1 − D ) L 1 0 0 0 0 0 D L 2 1 L 2 − ( 1 − D ) L 2 0 0 0 D L 3 − ( 1 − D ) L 3 0 − ( 1 − D ) C 1 D C 1 D C 1 0 0 0 0 1 − ( 1 − D ) C 2 0 0 0 0 − ( 1 − D ) C O 0 0 0 1 R , $$ A=\left[\begin{array}{cccccc}0& 0& 0& \frac{-\left(1-D\right)}{L_1}& 0& 0\\ {}0& 0& 0& \frac{D}{L_2}& \frac{1}{L_2}& \frac{-\left(1-D\right)}{L_2}\\ {}0& 0& 0& \frac{D}{L_3}& \frac{-\left(1-D\right)}{L_3}& 0\\ {}\frac{-\left(1-D\right)}{C_1}& \frac{D}{C_1}& \frac{D}{C_1}& 0&\ 0& 0\\ {}0& 1& \frac{-\left(1-D\right)}{C_2}& 0& 0& 0\\ {}0& \frac{-\left(1-D\right)}{C_O}& 0& 0& 0& \frac{1}{R}\end{array}\right], $$
B 1 = V C 1 L 1 V C 1 + V C 2 + V C O L 2 V C 1 + V C 2 L 3 I L 3 + I L 2 + I L 3 C 1 I L 3 C 2 I L 2 C O B 2 = 1 0 0 0 0 0 ; C = 0 0 0 0 0 1 ; D = 0 0 . $$ {B}_1=\left[\begin{array}{c}\frac{V_{C_1}}{L_1}\\ {}\frac{\left({V}_{C_1}+{V}_{C_2}+{V}_{C_O}\right)}{L_2}\\ {}\frac{V_{C_1}+{V}_{C_2}}{L_3}\\ {}\frac{\left({I}_{L_3}+{I}_{L_2}+{I}_{L_3}\right)}{C_1}\\ {}\frac{I_{L_3}}{C_2}\\ {}\frac{I_{L_2}}{C_O}\end{array}\right]\ {B}_2=\left[\begin{array}{c}1\\ {}0\\ {}0\\ {}0\\ {}0\\ {}0\end{array}\right];C=\left[0\kern0.5em 0\kern0.5em 0\kern0.5em 0\kern0.5em 0\kern0.5em 1\right];D=\left[\begin{array}{c}0\\ {}0\end{array}\right]. $$
The transfer function of the converter is given as,
v C O d ^ ^ = C ( sI − A ) − 1 B 1 + D . $$ \hat{\frac{v_{C_O}}{\hat{d}}}=C{\left( sI-A\right)}^{-1}{B}_1+D. $$ (38)

As in (22), the open-loop transfer function can be well obtained. The bode plot is depicted in Figure 12a with the corresponding control arrangement is shown in Figure 12b. The gain margin (GM) of the uncompensated system is infinite while it has a phase margin (PM) of 162.49°.

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FIGURE 12
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(a) Bode plot for the proposed DC-DC converter. (b) Control arrangement for a DC-DC converter.

4 Examination of the Suggested Converter Against Different Similar Topologies

The proposed buck-boost converter is compared to other converters, as presented in this section. It helps us to analyze its performance and establish its advantages over similar converters in the literature. Table 1 enlists the parameters which are taken into consideration for the comparison. The parameters include the number of inductors (NL), number of capacitors (NC), number of switches (NS), number of diodes (ND), and number of total components N T $$ \left({N}_T\right) $$ . Normally, a DC-DC converter is operated at lower duty ratios typically between 30% and 60% duty ratios. It is due to the fact that the switch stress increases as duty cycle is increased. The ideal voltage gains M CCM $$ \left({M}_{CCM}\right) $$ and its actual value and normalized value at 40% duty cycle are also taken into consideration while comparison. The duty ratio at which the converter achieves unity gain, the buck and boost efficiency ( η ) $$ \left(\eta \right) $$ of the converter, and whether the topology has a common ground (CG) and carries continuous input current (CIC) through the source is also enlisted. The normalized maximum semiconductor switch voltage stress V S max / V O $$ \left({V}_{S_{max}}/{V}_O\right) $$ , current stress I S max / I O $$ \left({I}_{S_{max}}/{I}_O\right) $$ , the normalized maximum diode voltage stress V D max / V O $$ {V}_{D_{max}}/{V}_O $$ , and current stress I D max / I O $$ \left({I}_{D_{max}}/{I}_O\right) $$ also brief about the switch design analysis for the various converters. The ideal gain of the selected topologies and effective gain comparison for the topologies are illustrated in Figure 13a,b, respectively. Some of the new key parameters consisting of maximum per-unit switching device power (SDP), passive component volume, the converter's cost factor, and the quantity of high-side and low-side switches are also considered. The SDP is obtained as the product of the maximum withstanding voltage and average conduction current.

TABLE 1. Comparison of various similar converters with the proposed converter.
Topology Reactive elements Semiconductor elements Total elements M CCM $$ {\boldsymbol{M}}_{\boldsymbol{CCM}} $$ M CCM $$ {\boldsymbol{M}}_{\boldsymbol{CCM}} $$ at D = 0.4 M CCM $$ {\boldsymbol{M}}_{\boldsymbol{CCM}} $$ per component at D = 0.4 D $$ \boldsymbol{D} $$ for unity gain η % $$ \boldsymbol{\eta} \% $$ for different modes CG/CIC
NL NC NS ND NT Buck Boost
TBBC 1 1 1 1 4 D 1 − D $$ \frac{D}{1-D} $$ 0.66 0.165 0.50 97.60 97.85 No/No
SEPIC 2 2 1 1 6 D 1 − D $$ \frac{D}{1-D} $$ 0.66 0.110 0.50 96.50 96.70 Yes/Yes
[13] 2 3 2 3 10 2 D ( 1 − D ) 2 $$ \frac{2D}{{\left(1-D\right)}^2} $$ 2.22 0.222 0.268 90.90 91.20 No/Yes
[14] 4 5 2 3 14 2 D ( 2 − D ) ( 1 − D ) 2 $$ \frac{2D\left(2-D\right)}{{\left(1-D\right)}^2} $$ 3.55 0.253 0.1835 93.55 93.80 Yes/No
[15] 2 2 1 3 8 D 2 1 − D $$ \frac{D^2}{1-D} $$ 0.266 0.033 0.625 96.00 96.20 No/No
[16] 2 2 2 2 8 D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2\ } $$ 1.11 0.138 0.3819 92.50 92.80 No/Yes
[17] 2 3 2 3 10 D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2} $$ 1.11 0.111 0.3819 89.80 90.00 Yes/Yes
[18] 2 2 2 2 8 D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2} $$ 1.11 0.138 0.3819 94.00 94.40 Yes/Yes
[19] 3 4 2 3 12 D ( 3 − D ) ( 1 − D ) 2 $$ \frac{D\left(3-D\right)}{{\left(1-D\right)}^2} $$ 2.88 0.240 0.219 90.85 91.00 Yes/No
[20] 3 3 2 2 10 D 1 − D 2 $$ {\left(\frac{D}{1-D}\right)}^2 $$ 0.435 0.043 0.5 91.85 92.00 Yes/Yes
[23] 3 3 2 4 12 2 D ( 1 − D ) 2 $$ \frac{2D}{{\left(1-D\right)}^2} $$ 2.22 0.185 0.268 94.30 94.50 No/Yes
[24] 2 1 3 2 8 2 D ( 1 − D ) $$ \frac{2D}{\left(1-D\right)} $$ 1.33 0.166 0.33 94.50 94.80 No/No
[25] 3 4 2 3 12 D ( 3 − D ) ( 1 − D ) 2 $$ \frac{D\left(3-D\right)}{{\left(1-D\right)}^2} $$ 2.88 0.240 0.219 92.10 92.40 No/Yes
Proposed 3 3 2 4 12 D ( 2 − D ) ( 1 − D ) 3 $$ \frac{\boldsymbol{D}\left(\mathbf{2}-\boldsymbol{D}\right)}{{\left(\mathbf{1}-\boldsymbol{D}\right)}^{\mathbf{3}}} $$ 2.96 0.246 0.2451 95.00 95.20 No/Yes
Topology M CCM $$ \left({\boldsymbol{M}}_{\boldsymbol{CCM}}\right) $$ V S max V O $$ \left(\frac{{\boldsymbol{V}}_{\boldsymbol{Smax}}}{{\boldsymbol{V}}_{\boldsymbol{O}}}\right) $$ I S max I O $$ \left(\frac{{\boldsymbol{I}}_{\boldsymbol{Smax}}}{{\boldsymbol{I}}_{\boldsymbol{O}}}\right) $$ V D max V O $$ \left(\frac{{\boldsymbol{V}}_{\boldsymbol{Dmax}}}{{\boldsymbol{V}}_{\boldsymbol{O}}}\right) $$ I D max I O $$ \left(\frac{{\boldsymbol{I}}_{\boldsymbol{Dmax}}}{{\boldsymbol{I}}_{\boldsymbol{O}}}\right) $$ Max. p.u. SDP Passive component volume CF at D = 0.4 High-side switches Low-side switches
TBBC D 1 − D $$ \frac{D}{1-D} $$ 1 D $$ \frac{1}{D} $$ 1 1 − D $$ \frac{1}{1-D} $$ 1 D $$ \frac{1}{D} $$ 1 $$ 1 $$ 1 D ( 1 − D ) $$ \frac{1}{D\left(1-D\right)} $$ 135.56 7.50 1 0
SEPIC D 1 − D $$ \frac{D}{1-D} $$ 1 D $$ \frac{1}{D} $$ D 1 − D $$ \frac{D}{1-D} $$ 1 D $$ \frac{1}{D} $$ 1 1 1 − D $$ \frac{1}{1-D} $$ 271.12 10.51 0 1
[13] 2 D ( 1 − D ) 2 $$ \frac{2D}{{\left(1-D\right)}^2} $$ 1 + D 2 D $$ \frac{1+D}{2D} $$ D ( 1 + D ) ( 1 − D ) 2 $$ \frac{D\left(1+D\right)}{{\left(1-D\right)}^2} $$ 1 + D 2 D $$ \frac{1+D}{2D} $$ 1 1 − D $$ \frac{1}{1-D} $$ ( 1 + D ) 2 2 ( 1 − D ) 2 $$ \frac{{\left(1+D\right)}^2}{2{\left(1-D\right)}^2} $$ 369.25 4.95 1 1
[14] 2 D ( 2 − D ) ( 1 − D ) 2 $$ \frac{2D\left(2-D\right)}{{\left(1-D\right)}^2} $$ 1 2 D ( 2 − D ) $$ \frac{1}{2D\left(2-D\right)} $$ 2 ( 1 − D ) 2 $$ \frac{2}{{\left(1-D\right)}^2} $$ 1 2 D $$ \frac{1}{2D} $$ 2 ( 1 − D ) 2 $$ \frac{2}{{\left(1-D\right)}^2} $$ 1 D ( 2 − D ) ( 1 − D ) 2 $$ \frac{1}{D\left(2-D\right){\left(1-D\right)}^2} $$ 640.38 4.22 1 1
[15] D 2 1 − D $$ \frac{D^2}{1-D} $$ 1 D 2 ( 1 − 2 D ) $$ \frac{1}{D^2\left(1-2D\right)} $$ D ( 1 − 2 D ) ( 1 − D ) $$ \frac{D\left(1-2D\right)}{\left(1-D\right)} $$ 1 D 2 ( 1 − 2 D ) $$ \frac{1}{D^2\left(1-2D\right)} $$ 1 D $$ \frac{1}{D} $$ 1 D ( 1 − D ) $$ \frac{1}{D\left(1-D\right)} $$ 271.12 33.75 0 1
[16] D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2\ } $$ 1 − D D $$ \frac{1-D}{D} $$ 1 ( 1 − D ) 2 $$ \frac{1}{{\left(1-D\right)}^2\ } $$ 1 − D D $$ \frac{1-D}{D} $$ 1 ( 1 − D ) 2 $$ \frac{1}{{\left(1-D\right)}^2\ } $$ 1 D ( 1 − D ) $$ \frac{1}{D\left(1-D\right)\ } $$ 271.12 8.10 1 1
[17] D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2} $$ 1 − D D $$ \frac{1-D}{D} $$ D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2\ } $$ 1 − D D $$ \frac{1-D}{D} $$ D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2\ } $$ 1 1 − D $$ \frac{1}{1-D} $$ 369.25 9.90 2 0
[18] D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2} $$ 1 D $$ \frac{1}{D} $$ D 1 − D 2 $$ {\left(\frac{D}{1-D}\right)}^2 $$ 1 D $$ \frac{1}{D} $$ D 1 − D $$ \frac{D}{1-D} $$ D ( 1 − D ) 2 $$ \frac{D}{{\left(1-D\right)}^2} $$ 271.12 8.10 1 1
[19] D ( 3 − D ) ( 1 − D ) 2 $$ \frac{D\left(3-D\right)}{{\left(1-D\right)}^2} $$ 1 D ( 3 − D ) $$ \frac{1}{D\left(3-D\right)} $$ D ( 1 + D ) ( 1 − D ) 2 $$ \frac{D\left(1+D\right)}{{\left(1-D\right)}^2} $$ 1 D ( 3 − D ) $$ \frac{1}{D\left(3-D\right)} $$ 1 + D 1 − D $$ \frac{1+D}{1-D} $$ ( 1 + D ) ( 3 − D ) ( 1 − D ) 2 $$ \frac{\left(1+D\right)}{\left(3-D\right){\left(1-D\right)}^2} $$ 504.82 4.51 1 1
[20] D 1 − D 2 $$ {\left(\frac{D}{1-D}\right)}^2 $$ 1 − D D 2 $$ \frac{1-D}{D^2} $$ D 1 − D 2 $$ {\left(\frac{D}{1-D}\right)}^2 $$ 1 − D D 2 $$ \frac{1-D}{D^2} $$ D 1 − D $$ \frac{D}{1-D} $$ 1 1 − D $$ \frac{1}{1-D} $$ 406.68 25.28 1 1
[23] 2 D ( 1 − D ) 2 $$ \frac{2D}{{\left(1-D\right)}^2} $$ 1 D $$ \frac{1}{D} $$ 2 D ( 1 − D ) 2 $$ \frac{2D}{{\left(1-D\right)}^2\ } $$ 1 D $$ \frac{1}{D} $$ 1 + D ( 1 − D ) 2 $$ \frac{1+D}{{\left(1-D\right)}^2\ } $$ 2 ( 1 − D ) 2 $$ \frac{2}{{\left(1-D\right)}^2\ } $$ 406.68 5.85 1 1
[24] 2 D ( 1 − D ) $$ \frac{2D}{\left(1-D\right)} $$ 1 − D 2 D $$ \frac{1-D}{2D} $$ 2 D 1 − D $$ \frac{2D}{1-D} $$ 1 + D 2 D $$ \frac{1+D}{2D} $$ D 1 − D $$ \frac{D}{1-D} $$ 1 $$ 1 $$ 173.00 6.76 2 1
[25] D ( 3 − D ) ( 1 − D ) 2 $$ \frac{D\left(3-D\right)}{{\left(1-D\right)}^2} $$ 1 + D D ( 3 − D ) $$ \frac{1+D}{D\left(3-D\right)} $$ 2 ( 1 − D ) 2 $$ \frac{2}{{\left(1-D\right)}^2} $$ 1 + D D ( 3 − D ) $$ \frac{1+D}{D\left(3-D\right)} $$ 1 + D ( 1 − D ) 2 $$ \frac{1+D}{{\left(1-D\right)}^2} $$ 2 ( 1 + D ) D ( 3 − D ) ( 1 − D ) 2 $$ \frac{2\left(1+D\right)}{D\left(3-D\right){\left(1-D\right)}^2} $$ 504.82 4.51 1 1
Proposed D ( 2 − D ) ( 1 − D ) 3 $$ \frac{\boldsymbol{D}\left(\mathbf{2}-\boldsymbol{D}\right)}{{\left(\mathbf{1}-\boldsymbol{D}\right)}^{\mathbf{3}}} $$ 1 D ( 2 − D ) $$ \frac{\mathbf{1}}{\boldsymbol{D}\left(\mathbf{2}-\boldsymbol{D}\right)} $$ D 2 ( 2 − D ) ( 1 − D ) 3 $$ \frac{{\boldsymbol{D}}^{\mathbf{2}}\left(\mathbf{2}-\boldsymbol{D}\right)}{{\left(\mathbf{1}-\boldsymbol{D}\right)}^{\mathbf{3}}} $$ 1 D ( 2 − D ) $$ \frac{\mathbf{1}}{\boldsymbol{D}\left(\mathbf{2}-\boldsymbol{D}\right)} $$ 1 ( 1 − D ) 2 $$ \frac{\mathbf{1}}{{\left(\mathbf{1}-\boldsymbol{D}\right)}^{\mathbf{2}}} $$ D ( 1 − D ) 3 $$ \frac{\boldsymbol{D}}{{\left(\mathbf{1}-\boldsymbol{D}\right)}^{\mathbf{3}}} $$ 406.68 4.39 1 1
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FIGURE 13
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(a) Comparison of ideal gain of various similar topologies. (b) Comparison of gain per element of various similar topologies.

The proposed topology produces a worthy gain during the buck mode, permitting the converter to be used for line driver and amplifier applications. The proposed converter achieves a reasonably high gain during its voltage boosting stage after the duty cycle of 24.51%. The converter can feed an output of four times the input voltage at a 50% switching cycle. Unlike the proposed topology, the TBB converter has a discontinuous input current, and its high boosted gain is restricted due to the converter's poor efficiency. The SEPI converter has a pulsating output current and generally requires large series capacitors and high current-handling capacities.

Figure 14a,b depict the normalized current and voltage stress handled by the switches during the converter's operation, respectively. The proposed converter and some similar converters have high switch voltage stress at lower duty ratios and high switch current stress at higher duty ratios. This makes the converter operation ideal for duty ratios between 20% and 55%. Similar parameters are also holistically evaluated in the reliability section of the paper.

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FIGURE 14
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(a) Comparison of normalized switch current stress of various similar topologies. (b) Comparison of normalized switch voltage stress of various similar topologies.

The converter proposed in [13] needs a common ground and is less efficient than the TBBC and proposed converter. The proposed converter, however, produces a higher gain with high efficiency and bears a lower voltage switching stress than [13]. The converter [14] has a common ground but discontinuous input current, inhibiting its applicability for renewable energy applications. Apart from its high gain and lower switching stress, the converter employs the highest number of elements among the compared topologies. The converters in [15, 16] lack the common ground, while the converter in [15] is also deficient in CIC. The converter [17, 18] has a reasonably high gain with a common ground, continuous input current, and lower element count; however, it operates at a low efficiency and has a higher switching stress at lower duty ratios. The converter proposed in [19] achieves high gain even at lower duty ratios but lacks CIC and produces lower gain than the proposed topology. The converter proposed in [23] has similar elements to the proposed topology; however, it produces a lower gain with lower efficiency and extremely high voltage stress across the switches.

As Figure 15a provides the required information about the maximum diode voltage stress experienced by the diodes in the respective converter, the proposed converter outperforms the stress-handling capability as compared to converters TBBC, SEPIC, [17-21, 24]. Furthermore, the proposed converter also has a lower cost factor than these converters, making it a preferable choice. Though the converters in [14, 25] offer lower diode stress and similar cost factor, they tend to consume tremendously higher switching power than the proposed converter. Figure 15b shows the maximum SDP sustained by the converter, where the SD of converter [23, 25] was found to be on the higher side for all duty ratios as compared to the proposed converter. The SDP of the converters shown in [14-17, 20] is higher for lower duty ratios and gradually decreases at higher duty ratios. Hence for lower duty ratio operations, which is generally the case, the proposed converter will be preferred over them. Furthermore, a lower duty ratio operation is preferred to maintain the converter's reliable operation, which will be discussed in the further sections.

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FIGURE 15
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(a) Comparison of normalized diode voltage stress of various similar topologies. (b) Comparison of the SDP of various similar topologies.

5 Reliability Assessment of the Proposed Converter

5.1 Improved Markov Model Analysis

The work acknowledges and uses the improved Markov model to assess the converter's reliability. The Markov reliability model studies the effect of faults encountered by suitable elements assuming a specified short-circuit (SC) probability. The passive components are prone to only SC faults, while semiconductor elements are studied for both OC and SC faults. In improved Markov modeling, the fault probability of the SC fault is considered as α s $$ {\alpha}_s $$ , and on the contrary, the open-circuit fault will be 1 − α s $$ \left(1-{\alpha}_s\right) $$ . Generally, the probability of SC is higher. Therefore, the value of αs is always more than 0.5. Figure 16 shows the improved Markov model chart for different states. State 1 represents the converter's desirable or healthy operation state. States 2 and 3 represent the operation in a partial power state where the converter operates at a derated state. State 4 corresponds to the absorbing or failure state without output.

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FIGURE 16
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Markov model representation for the proposed converter.
The reliability of the converter for “s” derated states is defined as,
R ( t ) = ∑ i = 1 s P i ( t ) , $$ R(t)=\sum \limits_{i=1}^s{P}_i(t), $$ (39)
where P i ( t ) $$ {P}_i(t) $$ is the probability of failure of the ith state. The probability function may be written as,
dP i ( t ) dt = P i ( t ) λ 11 λ 12 λ 13 λ 14 0 λ 22 0 λ 24 0 0 λ 33 λ 34 0 0 0 0 , $$ \frac{dP_i(t)}{dt}={P}_i(t)\left[\begin{array}{cccc}{\lambda}_{11}& {\lambda}_{12}& {\lambda}_{13}& {\lambda}_{14}\\ {}0& {\lambda}_{22}& 0& {\lambda}_{24}\\ {}0& 0& {\lambda}_{33}& {\lambda}_{34}\\ {}0& 0& 0& 0\end{array}\right], $$ (40)
where λ ij $$ {\lambda}_{ij} $$ represents the failure rate from state i $$ i $$ to state j $$ j $$ . We can hence obtain the generalized probabilities for different states as,
P i ( t ) = e λ ii t i = 1 λ 1 i λ 11 − λ ii e λ 11 − λ ii t i ≠ 1 . $$ {P}_i(t)=\left\{\begin{array}{ll}{e}^{\lambda_{ii}t}& i=1\\ {}\frac{\lambda_{1i}}{\lambda_{11}-{\lambda}_{ii}}{e}^{\left({\lambda}_{11}-{\lambda}_{ii}\right)t}& i\ne 1\end{array}\right.. $$ (41)
Initially, all the probabilities of derated and absorbing states are considered 0 for a fault-free operation of the converter.
P i ( 0 ) = 1 i = 1 0 i ≠ 1 . $$ {P}_i(0)=\left\{\begin{array}{ll}1& i=1\\ {}0& i\ne 1\end{array}\right.. $$ (42)
The MTTF of the converter is calculated by integrating the reliability function as,
MTTF = ∫ t = 0 ∞ R ( t ) dt . $$ MTTF=\int_{t=0}^{\infty }R(t)\ dt. $$ (43)

5.2 Fault Tolerability of the Converter

Fault interception in the converter deviates from the healthy operation. From Table 2, it is inferred that the output voltage decreases as the converter experiences a fault. The proposed converter leads to an absorbing state if the switch S 2 $$ {S}_2 $$ or any of the diode D 1 $$ {D}_1 $$ or D O $$ {D}_O $$ experiences any fault. Hence, the quality of these components must be ensured. An occurrence of OC fault in the switch S 1 $$ {S}_1 $$ or any fault across the diodes D 2 $$ {D}_2 $$ or D 3 $$ {D}_3 $$ keeps the converter in an operational state. However, faults in passive elements result in absolute failure of the converter.

TABLE 2. Effect of fault across elements on the output voltage.
Element Type of fault Derated voltage (%)
S 1 $$ {S}_1 $$ OC 59.96
SC Failure state
S 2 $$ {S}_2 $$ , D 1 $$ {D}_1 $$ , D O $$ {D}_O $$ OC or SC Failure state
D 2 $$ {D}_2 $$ OC 53.70
SC 38.15
D 3 $$ {D}_3 $$ OC or SC 38.15
L 1 $$ {L}_1 $$ , L 2 $$ {L}_2 $$ , L 3 $$ {L}_3 $$ , C 1 $$ {C}_1 $$ , C 2 $$ {C}_2 $$ , C O $$ {C}_O $$ SC Failure state

5.3 Reliability Assessment of the Converter Using Improved Markov Modeling

The failure rates for switches λ S $$ \left({\lambda}_S\right) $$ , diodes λ D $$ \left({\lambda}_D\right) $$ , and capacitors λ C $$ \left({\lambda}_C\right) $$ need to be computed using the equations [28, 29] in Table 3,
λ S = λ B . π T . π A . π Q . π E λ D = λ B . π T . π S . π C D . π Q . π E λ C = λ B . π T . π C . π V . π SR . π Q . π E λ L = λ B . π T . π Q . π E . $$ \left\{\begin{array}{l}{\lambda}_S={\lambda}_B.{\pi}_T.{\pi}_A.{\pi}_Q.{\pi}_E\\ {}{\lambda}_D={\lambda}_B.{\pi}_T.{\pi}_S.{\pi}_{C_D}.{\pi}_Q.{\pi}_E\\ {}{\lambda}_C={\lambda}_B.{\pi}_T.{\pi}_C.{\pi}_V.{\pi}_{SR.}{\pi}_Q.{\pi}_E\\ {}{\lambda}_L={\lambda}_B.{\pi}_T.{\pi}_Q.{\pi}_E\end{array}\right.. $$ (44)
TABLE 3. Expression for constants of failure rate for various elements.
Failure constant Switch Diode Capacitor Inductor
λ B $$ {\lambda}_B $$ 0.012 0.030 0.00037 0.000030
π T $$ {\pi}_T $$ exp − 1925 × 1 T J + 273 − 1 298 $$ \exp \left[\begin{array}{c}-1925\times \\ {}\left(\frac{1}{T_J+273}-\frac{1}{298}\right)\end{array}\right] $$ exp − 3091 × 1 T J + 273 − 1 298 $$ \exp \left[\begin{array}{c}-3091\times \\ {}\left(\frac{1}{T_J+273}-\frac{1}{298}\right)\end{array}\right] $$ exp − 1740 × 1 T + 273 − 1 298 $$ \exp \left[\begin{array}{c}-1740\times \\ {}\left(\frac{1}{T+273}-\frac{1}{298}\right)\end{array}\right] $$ exp − 1276.54 × 1 T HS + 273 − 1 298 $$ \exp \left[\begin{array}{c}-1276.54\times \\ {}\left(\frac{1}{T_{HS}+273}-\frac{1}{298}\right)\end{array}\right] $$
π A $$ {\pi}_A $$ 8 — — —
π Q $$ {\pi}_Q $$ 1 1 1 1
π E $$ {\pi}_E $$ 1 1 1 1
π S $$ {\pi}_S $$ — 0.71 exp ( 1.1 S ) $$ 0.71\ \exp (1.1S) $$ — —
π C D $$ {\pi}_{C_D} $$ — 1 — —
π C $$ {\pi}_C $$ — — C 0.09 $$ {C}^{0.09} $$ —
  • Note: λ B $$ {\lambda}_B $$ —Base failure rate, π T $$ {\pi}_T $$ —Temperature factor, π A $$ {\pi}_A $$ —Application factor, π Q $$ {\pi}_Q $$ —Quality factor, π E $$ {\pi}_E $$ —Environmental factor, π S $$ {\pi}_S $$ —Electrical stress factor, π C D $$ {\pi}_{C_D} $$ —Contact construction factor, π C $$ {\pi}_C $$ —Capacitance factor, π V $$ {\pi}_V $$ —Voltage stress factor, π SR $$ {\pi}_{SR} $$ —Series resistance factor, T J $$ {T}_J $$ —junction temperature, T—capacitor ambient temperature, T HS $$ {T}_{HS} $$ —hotspot temperature, S—Active power dissipation/Rated power.
The failure rates of the components as per the improved Markov model are shown in Table 3, and the equivalent factors for the converter element are given as,
λ 12 = 1 − α S λ S λ 13 = 1 − α S λ D λ 14 = λ S + 2 + α S λ D + 2 λ C + λ CO + 3 λ L λ 24 = λ S + 2 − α S λ D + 2 λ C + λ CO + 3 λ L λ 34 = 1 + α S λ S + 3 − α S λ D + 2 λ C + λ CO + 3 λ L , $$ \left\{\begin{array}{l}{\lambda}_{12}=\left(1-{\alpha}_S\right){\lambda}_S\\ {}{\lambda}_{13}=\left(1-{\alpha}_S\right){\lambda}_D\\ {}{\lambda}_{14}={\lambda}_S+\left(2+{\alpha}_S\right)\ {\lambda}_D+2{\lambda}_C+{\lambda}_{CO}+3{\lambda}_L\\ {}{\lambda}_{24}={\lambda}_S+\left(2-{\alpha}_S\right){\lambda}_D+2{\lambda}_C+{\lambda}_{CO}+3{\lambda}_L\\ {}{\lambda}_{34}=\left(1+{\alpha}_S\right){\lambda}_S+\left(3-{\alpha}_S\right){\lambda}_D+2{\lambda}_C+{\lambda}_{CO}+3{\lambda}_L\end{array}\right., $$ (45)
R ( t ) = e − 0.442 − 0.014 α S t − 1 − α S α S + 0.995 e − 0.206 α S + 0.205 t − 1 − α S 1.208 α S + 0.854 e − 0.249 α S + 0.176 t , $$ {\displaystyle \begin{array}{cc}R(t)& ={e}^{-\left(0.442-0.014{\alpha}_S\right)t}-\frac{1-{\alpha}_S}{\alpha_S+0.995}{e}^{-\left(0.206{\alpha}_S+0.205\right)t}\\ {}& \kern1em -\frac{1-{\alpha}_S}{1.208{\alpha}_S+0.854}{e}^{-\left(0.249{\alpha}_S+0.176\right)t},\end{array}} $$ (46)
MTTF = 1 0.263 α S − 0.265 + 1 − α S 0.442 − 0.014 α S 1.208 α S + 0.854 + 2 0.442 − 0.014 α S + 1 − α S 0.22 α S − 0.237 α S + 0.995 years failure . $$ {\displaystyle \begin{array}{cc} MTTF& =\frac{1}{0.263{\alpha}_S-0.265}+\frac{1-{\alpha}_S}{\left(0.442-0.014{\alpha}_S\right)\left(1.208{\alpha}_S+0.854\right)}\\ {}& \kern1em +\frac{2}{\left(0.442-0.014{\alpha}_S\right)}+\frac{1-{\alpha}_S}{\left(0.22{\alpha}_S-0.237\right)\left({\alpha}_S+0.995\right)}\frac{years}{failure}.\end{array}} $$ (47)

The converter's reliability and MTTF for any viable case can be easily obtained by varying the SC probability. For an SC probability of 75%, the MTTF of the converter is 5.743 years/failure, whereas for an SC probability of 85%, the MTTF is obtained as 5.647 years/failure.

5.4 Variation of Reliability and MTTF of the Converter

In the current section of the paper, the effect of different converter parameters on the converter's reliability is discussed. The reliability and MTTF of the proposed converter decrease as the SC probability (αs) of the semiconductor devices overpowers the OC probability, as shown in Figure 17a. The reliability of the converter increases as the open-circuit fault probability decreases. It is due to the reason that the converter inhibits further operation if the elements like S 2 $$ {S}_2 $$ , D 1 $$ {D}_1 $$ , or D 2 $$ {D}_2 $$ are open-circuited while it continues its operation as D 2 $$ {D}_2 $$ or D 3 $$ {D}_3 $$ is short-circuited. The converter is still 55% reliable after half a million hours or approximately five decades of operation for 70% SC probability, while it decreases to 44% as the converter reaches its centenary operation. Conversely, the MTTF lies above 6 years if the SC probability is around 60%, as shown in Figure 17b. The reliability is evaluated and presented in the form of 3D graphs where different converter parameters are varied over time.

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FIGURE 17
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(a) Variation of Reliability of the converter with time as the SC probability is varied. (b) Variation of MTTF of the converter with SC probability.

5.4.1 Effect of Duty Cycle (D)

The duty cycle of the switch can be varied to achieve the required rated voltage at the output. Therefore, assessing the behavior of the converter's reliability with duty ratio as per the equations in [22, 23] helps us to choose an optimized converter for the specified application. Figure 18a shows that continuous operation of the converter at extremely low or extremely high duty ratios can harm the converter's reliability. This is because the switch operates under maximum stress for lower duty ratios. The converter operates optimally around a 50% duty ratio with maximum permissible reliability. The converter is 60% reliable after continuous operation at a 50% duty ratio, even after five decades of operation, assuming a 70% short-circuit probability. On the other hand, Figure 18b shows that the MTTF of the converter also has the same normalized behavior with an optimal value of 7 years per failure at around 45% duty ratio for 70% short-circuit probability.

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FIGURE 18
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(a) Variation of Reliability with time and Duty Ratio (D). (b) Variation of MTTF with Duty Ratio (D) as αs is increased.

5.4.2 Effect of Input Voltage

The buck-boost converter will provide a higher gain at the output as the input voltage increases. However, it will also result in higher stress across the active and passive components, eventually perniciously affecting the converter's life. Therefore, applying a calculated input voltage decided by the application will result in improved and reliable operation of the converter over time, which can be obtained from equations in [22, 23]. Figure 19a shows that the converter's reliability reduces slightly as the input voltage increases. On the other hand, the MTTF observes an instead intercepted linear change with the rise in input voltage. The converter can handle around 12 years per failure as the converter operates at a 60 V input voltage even if the short-circuit probability of the active elements is near unity. Though a lower kept input voltage will increase the reliability and MTTF, it would also lead to higher duty-cycle operation to achieve the rated output voltage. Hence, a slightly higher voltage is preferred, even at lower reliability. For a voltage operation of about 40 V at which the converter achieves an efficiency of 95.2%, the converter is 70% reliable after seven decades of operation and has an MTTF of over 12 years per failure for 80% short-circuit probability as depicted in Figure 19b.

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FIGURE 19
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(a) Variation of Reliability with time and Input Voltage (Vin). (b) Variation of MTTF with Input Voltage (Vin) as αs is increased.

5.4.3 Effect of Output Power

The efficiency of the proposed nonisolated converter is affected drastically as the converter feeds higher power. This limits the usage of the converter for low- to medium-power applications. Various isolated converters [6, 8, 9] are in the literature for high-power applications. The proposed converter operates at a reliability of 70% after 0.6 million hours of operation when operated at 100 W, achieving an MTTF of 12.25 years per failure, as shown in Figure 20a,b.

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FIGURE 20
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(a) Variation of Reliability with time and Output Power (PO). (b) Variation of MTTF with Output Power (PO) as αs is increased.

6 Experimental Evaluation

The experimental hardware results of the 50/200 W prototype of the proposed buck-boost converter topology for different switching cycles are presented in this section. The results verify the theoretical analysis of the converter and analyze its practical functionality. The results are presented while the converter is operated at 20%, 40%, 60%, and 80% duty ratios. Figure 21 shows the experimental prototype setup and the respective specifications of the elements in the prototype are mentioned in Table 4. A frequency of 30 kHz is provided to the switches by the means of the microcontroller. The inductor current ripples are limited to below 35% for the CCM operation at higher duty cycles. The suitable experimental results hence obtained are illustrated in Figure 22a–h. The experimental results for the buck mode of operation for 20% duty cycle are depicted in Figure 22a,b. The boost mode experimental signatures for the converter are presented for three duty cycles (40%, 60%, and 80%) in Figure 22c–h.

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FIGURE 21
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Experimental prototype setup of the proposed topology.
TABLE 4. Experimental values of various parameters of elements used in the converter.
Parameter Symbol Specification
Input voltage V in $$ {V}_{in} $$ 20 V
Duty cycle D $$ D $$ 0.2, 0.3, 0.4, 0.6, 0.8
Output power P O $$ {P}_O $$ 50 W (Buck Mode), 200 W (Boost Mode)
Load R O $$ {R}_O $$ 50–300 Ω
Inductors L 1 $$ {L}_1 $$ 1 mH, ESR = 0.14 Ω
L 2 $$ {L}_2 $$ , L 3 $$ {L}_3 $$ 0.7 mH ESR = 0.10 Ω
Capacitors C 1 − C 2 $$ {C}_1-{C}_2 $$ 50 μF, ESR = 0.1 Ω
C O $$ {C}_O $$ 100 μF, ESR = 0.22 Ω
Diodes D O to D 3 $$ {D}_O\ to\ {D}_3 $$ 1 N7408
Power MOSFETs S 1 $$ {S}_1 $$ , S 2 $$ {S}_2 $$ SPW52N50C3
Driver TLP250H
Controller FPGA
Switching frequency f s $$ {f}_s $$ 30 kHz
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FIGURE 22
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Various Experimental evaluation of the proposed converter. (a) (Top to Bottom) Output voltage, Capacitor voltage, and Input voltage at duty ratio of 20%. (b) (Top to Bottom) Output current and Inductor current at duty ratio of 20%. (c) (Top to Bottom) Output voltage, Capacitor voltage, and Input voltage at duty ratio of 40%. (d) (Top to Bottom) Capacitor voltages and switching stress at duty ratio of 40%. (e) (Top to Bottom) Inductor currents at duty ratio of 40%. (f) (Top to Bottom) Output voltage, Capacitor voltage, and Input voltage at duty ratio of 60%. (g) (Top to Bottom) Capacitor voltages and switching stress at duty ratio of 60%. (h) (Top to Bottom) Input voltage, Output voltage, and switching stress at duty ratio of 80%.

6.1 Buck Mode Operation

Figure 22a depicts the output voltage waveform across capacitor C1 while the switch is driven at a 20% duty ratio at 20 V input. The converter operates in buck mode as the duty ratio is below 24.51%. An output of 12 V is obtained which is 14.28% lesser than the ideal output. The voltage across capacitor C1 is obtained as 22 V which is 12% lower than its ideal value. Figure 22b, on the other hand, depicts an output current of 4 A flowing through the resistive load when the input is kept at 20 V input. The inductor L1 is also observed to be operating near the boundary conditions with a maximum current of 6 and 5.8 A of ripple current. An average current of 3.1 A flows through the inductor under the aforementioned conditions. From the experimental results, at 20% duty ratio, the voltage source delivers 62 W of power and the converter feeds 48 W at the output. The working efficiency of the converter can hence be formulated as 77.42%.

6.2 Boost Mode Operation

As shown in Figure 22c, the gate voltage of 20 V is supplied to achieve a duty cycle of 40%, with an output of 52 V is obtained at the load. The output is depreciated by 12.25% than the ideal voltage. The capacitor C1 sustains a voltage of around 32 V, while capacitors C2 and CO have a voltage of 18 and 52 V, respectively, as shown in Figure 22d. The practical voltage across the capacitors C1, C2, and CO drops by 4%, 19%, and 13.3%, respectively, as compared to their ideal counterpart. The switches S1 and S2 withstand a voltage of 32 and 88 V, respectively, across them during their turned OFF state. The inductor L2 carries a continuous current with a maximum value of 14.4 A and a minimum of 7.2 Awith an average current of 10.8 A flowing through it, as shown in Figure 22e. The inductor sustains a current ripple of 33.33% which can be further reduced by increasing the switching frequency or optimizing the PCB layout. The inductor L3, on the other hand, experiences a maximum current of 22 A and a minimum current of 14 A, with an average of 18 A flowing through it. The inductor sustains a current ripple of 22.22%, which is well within the prescribed range.

Figure 22f depicts the output and input voltage waveform with gate-to-source voltage at a 60% duty cycle. At the output across the resistor at 20 V input, 210 V is produced. The converter's output is 10.5 times the input voltage, which is 20% less than the ideal gain of the suggested converter. The voltages across the capacitors C1 and CO stand at 43 and 210 V, respectively, as shown in Figure 22f. The capacitors operate at a voltage 14% and 19.8% less than their ideal values. The switches bear a voltage stress of 50 and 260 V, respectively, during their OFF states as shown in Figure 22g. The capacitor C2 also works at a voltage of 60 V, which is 20% lower than that of its ideal counterpart.

Figure 22h shows the converter's extreme duty ratio operation at 80% duty ratio, wherein the converter produces 225 V output voltage, approximately 10% of the ideal gain. Hence, the converter is inhibited from performing extreme duty ratio operations.

7 Simulative Evaluation of the Converter for Dynamic Conditions

As discussed in the previous section, the converter performs effectively in the static experimental operation. The current section discusses the dynamic simulative operation of the converter under varying input voltage, variable duty ratio, and fluctuating load conditions. The varying input voltage will depict the input fluctuations' handling of the converter when it is employed for solar photovoltaic applications. Initially, the converter is operated at 20 V, with a 40% duty cycle at a 100 Ω load. The conditions are kept after 2 s when the suitable variations are surpassed. Figure 23 shows the parametric variations considered during the converter's dynamic analysis. At 0.5 s, the converter's behavior is assessed only for the input voltage variation from 20 to 30 V, while a change in both the load and the duty cycle is depicted after a second is passed from the start. After 2 s, when the converter returns back to the initial conditions, a change in all three parameters is observed.

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FIGURE 23
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Overview of the parametric variations considered during dynamic operation of the proposed converter.

The equivalent behavior of the converter with the aforementioned parametric variations can be seen in Figure 24a,b. Figure 24a shows the variation in the input current and power, while the adjustment of the output voltage, output current, and output power as the parameters transcend can be observed in Figure 24b. The disturbances and oscillations produced in the respective currents and power of the input and output terminals of the converter can be managed and limited by employing suitable control circuits.

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FIGURE 24
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(a) Input Voltage, Input Current, and Input Power under dynamic conditions. (b) Input Voltage, Input Current, and Input Power under dynamic conditions.

8 Discussion and Conclusions

The suggested buck-boost converter provides a unity gain at 24.51% duty cycle and a cubic gain of six times the TBBC at 50% duty cycle with reduced switching stress and increases the boost operating region of the converter for equivalent microgrid application. The converter has a maximum working efficiency of 95.2% at 100 W output power when powered by a 40 V source in the boost region while an efficiency of 95.00% under buck operation. Furthermore, with a twin active switch operation of the converter, following the same duty cycle provides better reliability as the converter offers a derated output even when a switch S1 experiences an OC fault. The converter also does not use transformers or connected inductors, eliminating the possibility of inductive leakage problems and improving dependability. The converter also offers a common ground and continuous input current at lower duty ratios, making it suitable for renewable and DC microgrid applications.

Author Contributions

Ifham H. Malick: methodology, investigation, formal analysis, conceptualization, writing – original draft, software, data curation, visualization. Mohammad Zaid: conceptualization, methodology, supervision, writing – review and editing, software, project administration, data curation, visualization, resources. Javed Ahmad: validation, writing – review and editing, resources. Chang-Hua Lin: writing – review and editing. Marwan Ahmed Abdullah Alasali: funding acquisition.

Acknowledgments

The authors have nothing to report.

    Conflicts of Interest

    The authors declare no conflicts of interest.

    Data Availability Statement

    Data sharing not applicable to this article as no datasets were generated or analysed during the current study.

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