Volume 67, Issue 1 pp. 111-118
Article
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Stacked analog—I2L LSI

Kenji Kaneko

Kenji Kaneko

Central Research Laboratory, Hitachi Ltd., Kokubunji, Japan 185

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Takahiro Okabe

Takahiro Okabe

Central Research Laboratory, Hitachi Ltd., Kokubunji, Japan 185

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Minoru Nagata

Minoru Nagata

Central Research Laboratory, Hitachi Ltd., Kokubunji, Japan 185

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Setsuo Ogura

Setsuo Ogura

Takasaki Work, Hitachi Ltd., Takasaki, Japan 370-11

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Makoto Furihata

Makoto Furihata

Takasaki Work, Hitachi Ltd., Takasaki, Japan 370-11

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Keizo Matsumoto

Keizo Matsumoto

Hitachi Microcomputer Engineering Ltd., Kodaira, Japan 187

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Abstract

Recently, with the advance of microfabrication techniques, extremely many circuits are integrated in a silicon chip. As a result, the power density is increased and the processing of this power density becomes a key to realize a VLSI. As a means to resolve this problem, this paper discusses a method for reducing the power consumption in the entire analog-digital LSI by resuing in the I2L circuit, the current already used in the analog circuit. Several representative analog circuits are studied in this paper and a stacking of the analog circuit and the I2L circuit is investigated. As an example, when an I2L circuit is combined in the constant current souce side of the differential amplifier with the signal gain of 36 dB, the noise leakage from the I2L circuit to the output of the differential amplifier is about -14 dB (about 2 mV). This stacked analog -I2L is applied to an actual integrated circuit. Without losing the function and characteristics of the original integrated circuit the apparent power consumption of the I2L circcuit is made zero and the power consumption of the entire integrated circuit is reduced from 65 mW to 34 mW, which is about a 50% reduction.

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