Chapter 7

Transmitter Linearization with Digital Predistorters

First published: 20 December 2024

Summary

This chapter aims to provide an overview of diverse linearization strategies, whose design rests on the foundations laid in the previous chapters of the book. The nonlinearity versus efficiency trade-off posed by the power amplifier in communication transmitters is tackled by the addition of a system, the digital predistorter, that produces a linearized output of the cascade formed by itself and the power amplifier. The concept of digital predistortion is elaborated along with its repercussions for the underlying implementation architectures, the most common of them being the direct learning architecture and the indirect learning architecture. The regression that is involved in the design of the predistorter for both architectures is combined with the use of sparse machine learning techniques. To wrap up the chapter, an extensive set of predistortion scenarios with experimental results is provided to exemplify its application.

The full text of this article hosted at iucr.org is unavailable due to technical difficulties.