This paper aims to propose, study, and implement a non-isolated trans-inverse high step-up SEPIC-based DC-DC converter for photovoltaic applications. To increase the output voltage level, the presented configuration utilizes a three-winding coupled inductor and an improved voltage multiplier cell. However, unlike other coupled inductor-based DC-DC structures, the voltage gain could be enhanced by raising and lowering the secondary and tertiary winding turns ratio, respectively. Furthermore, a passive voltage clamp is employed to reduce the voltage stress on the switch and recover the energy stored in the leakage inductance of the coupled inductor. Hence, a switch with low RDS-ON could be used. Thanks to the soft switching performance of all diodes, their reverse recovery problem is eliminated. The outstanding merits of the converter such as continuous input current and high efficiency make the presented structure a promising solution for photovoltaic applications. In the end, the proposed converter is compared to different types of DC-DC converters to prove its advantages over the converters designed before. To confirm the converter’s performance and theoretical analysis, a 200 W laboratory prototype is implemented that steps up an input voltage of 25 V to an output voltage of 400 V at the switching frequency of 50 kHz. Experimental results are illustrated. At the end, the experimental results are presented to validate the analyses conducted.

1. Introduction

Global fossil fuel consumption has not reached the pick yet. However, they are non-renewable resources and come with severe negative environmental impacts such as local air pollution and global climate changes. Therefore, it is needed to transition away from fossil fuels. Technological advances, lower costs for photovoltaic (PV) systems, and various financial incentive schemes have helped to spread of PV systems since the mid-1990s. High reliability, low maintenance cost and noise, environmental friendliness, and zero emission are some merits of PV systems [1, 2].

Various references have addressed the main criteria for designing promising DC-DC configurations for PV-based systems. High gain and efficiency, low volume and weight, and common shared ground between the source, the switch, and the load are the most noticeable ones [3–5]. Draining continuous current with minimum ripple from the input PV source is the other imperative in designing DC-DC structures for PV systems. This feature minimizes errors of maximum power point tracking (MPPT) algorithms [6]. In [7, 8], a couple of non-isolated DC-DC configurations have been presented. An inductor is in series with the input voltage source to provide low-ripple input current. However, the voltage conversion ratio is still low, making them unsuitable for PV applications.

Utilizing non-isolated DC-DC converters greatly expands due to their performance in higher conversion ratios, lower cost and size, and lower voltage stresses on switches and diodes [9, 10]. Non-isolated converters are derived from either single-stage structures such as buck, boost, and buck-boost converters or two-stage topologies like single-ended primary-inductor converter (SEPIC), Ćuk and Zeta converters [11, 12].

In recent references, authors have employed various techniques to increase the voltage gains of DC-DC converters. Switched capacitors and inductors, voltage lift, and voltage multiplier (VM) cells are some of them [13, 14]. Another method to increase the voltage gain of DC-DC converters is utilizing two-winding and three-winding coupled inductors (CIs). In [15], a SEPIC-based DC-DC converter that employs a two-winding CI is studied. Continuous input current and high step-up voltage gain are the main advantages of the presented converter. In [16–18], authors have presented three DC-DC converters based on the two-winding CI. Unlike most CI-based converters, the voltage conversion ratio is increased by reducing their magnetic turns ratio. However, their voltage gain is still low for PV systems.

In [19–21], a triple of DC-DC converters based on three-winding CIs and VM cells has been studied. All three converters have high voltage gain. However, they suffer from high input current ripple. Thus, it would be difficult to utilize an efficient MPPT algorithm to control the system. Authors in [22, 23] have presented other three-winding CI-based DC-DC converters. Continuous input current is achieved by employing an input inductor in series with the voltage source.

In [24–28], various DC-DC converters based on trans-inverse three-winding CIs have been presented. Converters in [24, 25] are also based on the SEPIC structure. Meanwhile, soft switching performances of switches and diodes have been achieved. In [26], a high step-up trans-inverse DC-DC converter has been presented. Zero voltage switching (ZVS) was achieved at the switch’s turn-on time. However, utilizing two switches increases the complexity of the converter. Authors have studied a modified DC-DC converter based on the switched capacitor in [27]. High voltage gain and continuous input current are the main advantages of the converter. However, the voltage conversion ratio is relatively low regarding the number of components. Another SEPIC-based DC-DC converter has been presented in [28]. The converter efficiency is improved by utilizing quasi-resonance operation. However, voltage gain needs to be increased further.

This paper studies a new high step-up non-isolated DC-DC converter. The proposed converter is drafted from the conventional SEPIC structure. Thus, it benefits from the continuous input current feature of SEPIC topology. As an inductor is in series with the input source, continuity of the input current is guaranteed. However, some other three-winding CI-based DC-DC converters such as structures presented in [19–21] lack this feature, making them unsuitable for PV-based applications. A three-winding CI is used to raise the voltage gain. Voltage gain could be improved by raising and lowering the secondary and tertiary windings turns ratio, respectively. The name “Trans-inverse” is used to represent this inverse operating principle of converter [16]. Moreover, an improved VM cell is utilized to increase the voltage conversion ratio of the converter. Unlike most DC-DC converters presented before, the VM cell is charged by both the primary and the secondary sides of the CI. Hence, compared to other trans-inverse-based structures, the designed converter achieves higher voltage gains in the same duty ratio. Meanwhile, shared common ground between input, output, and switch results in reduced common noise, improved gate driving, and enhanced overall stability and performance of the converter. A passive voltage clamp is also utilized which recycles the energy stored in the leakage inductance of the CI and clamps the voltage stress on the switch. Therefore, a low on-resistance (R_DS−ON) switch can be used, reducing cost and conduction losses and increasing efficiency. Besides, thanks to the soft switching performance of all semiconductors, the converter efficiency is enhanced significantly. As the voltage stress of the output diode is relatively low and all diodes are reverse-biased under zero current switching (ZCS) conditions, reverse recovery problems of all diodes are entirely alleviated. The converter is compared to several DC-DC converters in terms of voltage gain, voltage stresses on semiconductors, and the ease of utilizing the MPPT algorithm. In the final analysis, a 200 W laboratory prototype of the converter is implemented and its functionality is verified by experimental results.

2. Operating Principles and Steady State Analysis of the Proposed Converter

Figure 1 shows the equivalent circuit of the presented structure. As depicted in this figure, the presented structure consists of a switch S, an inductor L_in, one three-winding CI with turns ratios of n₂ and n₃, five capacitors C₁ − C₄ and C_o, and four diodes D₁ − D₄. L_k and L_m represent leakage and magnetizing inductances of the CI, respectively. N₁, N_2, and N₃ symbolize primary, secondary and tertiary winding turn numbers of the CI, respectively. Voltage stress on the switch is clamped by the capacitor C₂ and the diode D₁. Hence, energy stored in the leakage inductance of the CI is recycled and a switch with low R_DS−ON could be utilized. Moreover, both primary and secondary windings of the CI charge the capacitors in the VM cell. Besides, the switch turns on and all diodes turn off under ZCS conditions. Hence, reverse recovery problems of all diodes are solved.

Details are in the caption following the image — **Figure 1**
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The equivalent power circuit of the proposed DC-DC converter.

To simplify the steady-state analysis of the proposed converter, the following assumptions are assumed: (1) All capacitors and inductors are large enough without any ripplein their voltages and currents, respectively. (2) The switch and diodes are ideal without parasitic components. The operation principle of the proposed structure in continuous conduction mode (CCM) includes five intervals. Current flow paths and main waveforms of operating modes are depicted in Figures 2 and 3, respectively. It is worth noting that Figure 3 shows only the waveforms’ trends and does not give their values.

2.1. Mode I [t₀ − t₁]

This mode begins when switch S is turned on under the ZCS condition at t = t₀. Diodes D₂ and D₄ are still on, while diodes D₁ and D₃ are off. The leakage inductance of the CI decreases the slope of the current flowing through the switch (di_s/dt) at the turn-on instant. Input inductor L_in is. Charged by the input voltage. Meanwhile, the primary and the secondary sides of the CI charge the capacitor C₃ During this mode, the energy stored in the leakage inductance of the CI is recycled and transferred to the capacitor C₂. The current flowing through the secondary side of the CI is approaching zero. When it reaches zero, this mode ends. Figure 2(a) shows the relative current-flow path of this mode.

2.2. Mode II [t₁ − t₂]

At the beginning of this mode, diodes D₂ and D₄ turn off under ZCS conditions. Since the direction of the current flowing through the secondary side of the CI is reversed, diode D₂ turns on at ZCS condition, as well. Switch S remains on and the input source charges the inductor L_in like mode I. Capacitor C₁ and the CI are charged by capacitor C₂ through the switch S. Meanwhile, the primary and secondary sides of the CI along with capacitor C₃ charge capacitor C₄. The output capacitor C_o supplies the load. This mode ends when the switch S is turned off. Figure 2(b) shows the relative current-flow path. Currents flowing through the capacitors could be given by:

()

Moreover, the following equations could be obtained:

()

Where

and

are voltage and current of the leakage inductance L_k in mode II, respectively and given by:

()

2.3. Mode III [t₂ − t₃]

At t = t₂, switch S is turned off and clamp diode D₁ is forward-biased as depicted in Figure 2(c). Thus, the voltage across switch S is clamped to the voltage of capacitor C₂. Moreover, energy stored in the leakage inductance of the CI is recycled through capacitor C₁ and diode D₂. Diode D₃ remains on. The energy of input inductor L_in is transferred to the capacitor C₂. Like the previous mode, the output capacitor C_o supplies the load and the primary and the secondary sides of the CI along with capacitor C₃ charge capacitor C₄. This mode ends when the current flowing through the secondary side of the CI reaches zero. Currents of diodes D₁ and D₃ could be formulated as:

()

Where i_L2 is given by:

()

2.4. Mode IV [t₃ − t₄]

At t = t₃, diode D₃ turns off under ZCS conditions. At this time, the direction of current flowing through the secondary side of the CI is reversed. Hence, diodes D₂ and D₄ are forward-biased under ZCS. Diode D₁ remains on. Recycling energy of the leakage inductance of the CI is continued in this mode. The energy stored in inductor L_in is transferred to the capacitor C₂. The primary and the secondary sides of the CI charge the capacitor C₃. Figure 2(d) shows the relative current-flow path of this mode. The following equations can express currents flowing through the capacitors in this time interval:

()

Furthermore, the following equation could be achieved for the current flowing through the diode D₁:

()

Applying Kirchhoff’s voltage law on the circuit yields to:

()

Where

represents voltage across leakage inductance of the CI in mode IV. This voltage could be calculated from:

()

Where d₄ is the period of mode IV and

represents the current of the leakage inductance of the CI in mode IV and given as:

()

2.5. Mode V [t₄ − t₅]

The last mode begins when clamp diode D₁ is reverse biased under the ZCS condition at t = t₄. In this mode, switch S and diode D₃ remain off. Diodes D₂ and D₄ are forward-biased. Capacitor C₂ is charged by both the primary and the secondary sides of the CI. Meanwhile, energy stored in the input inductor and the CI along with the voltage.

Source charge the output capacitor C_O and provide energy for the load. The input current decreases linearly like mode IV. Figure 2(e) shows the relative current-flow path of this mode.

Neglecting the current ripple of the inductor L_in and magnetizing inductance of the CI, the current slope of leakage inductance of the CI along with diodes D₂ and D₄ are almost zero. Thus, the voltage across the leakage inductance of the CI is zero. Assuming that capacitors are large enough, currents of diodes D₂ and D₄ are equal. The following equations can be achieved.

()

Where i_L2 is the current flowing through the secondary side of the CI and equals to:

()

To simplify the steady-state analysis of the presented converter, short transitions that happen during one complete switching period (modes I and III) could be ignored. By applying volt-second balance principles on the inductors in different modes, the following equations can be achieved.

()

Neglecting the leakage inductance of the CI along with substituting (26)–(28) into (6), (18), and (19), the ideal voltage conversion ratio of the proposed converter could be obtained as follows:

()

To achieve the real voltage gain of the presented converter, the duration of mode IV, and the voltage across the leakage inductance of the CI in modes II and IV should be calculated. Assuming that currents flowing through input, output and magnetizing inductance of the CI are ripple free, by applying ampere-second balance principles on the capacitors, it could be proved that the average values of diode currents are equal to the output current I_o. According to Figure 3, the average current of diode D₃ could be formulated as:

()

Hence, the voltage across the leakage inductance of the CI in mode II could be obtained as:

()

Where f_S and R_L are the switching frequency and load, respectively. Applying ampere-second balance principles on the capacitor C₁ yields to:

()

Duration of mode IV could be calculated by using the average current of diode D₃ as follows:

()

Substituting (31) and (33) into (28) yields to:

()

By substituting (26), (27), and (28) into (6) and (18), the voltages of capacitors C₃ and C₄ could be calculated as:

()

Real voltage gain could be formulated by using (33) and (34) along with substituting (27), (35), and (36) into (19) as follows.

()

Where G_CCM is the real voltage gain of the converter. Supposing that L_k = 0, Q is zero, and (37) will be equal to (29).

3. Design of the Proposed Converter

According to [15], drawbacks of discontinuous conduction mode include slow dynamic response, high current stress of switch and diodes, dependence of the structure on frequency, structure on frequency, output power, and the value of inductors. Hence, values of inductors have to be selected with the purpose of operating the converter in CCM. Hence, to operate the converter in CCM, average current value of inductors L_in and L_m have to be more than half of their ripples. The instantaneous value of the input current can be expressed as follows:

()

In CCM operation mode, when the switch is on, the input current increases, and when the switch is turned off, it returns to its initial value. Therefore, the ripple of the input current is equal to:

()

Hence, the input current ripple could be given by:

()

Using a similar method, the ripple in the inductance of the coupled inductor is obtained as follows.

()

To guarantee the converter’s CCM operation, the inductor L_in’s selected value should satisfy the following conditions.

()

If the converter operates in boundary conduction mode, currents of input and magnetizing inductance of the CI will be equal at the end of the switching period [15]. It yields to:

()

Therefore, in case the following condition is satisfied, the proposed converter will operate in CCM mode.

()

Substituting (29), (32), (40) and (41) into (44) yields to:

()

The conversion ratio of the proposed converter could be controlled by changing the duty cycle D and turn ratios of the CI. Utilizing (29), the following expressions could be achieved.

()

In designing CI, n₂ and n₃ have to be more than zero (n₂ > 0 and n₃ > 0). Moreover, according to (29), n₃ < 1 is necessary for achieving positive voltage gain. Hence, ranges of turn ratios of the CI could be formulated as follows.

()

Mathematically, the higher the value of n₂ and the closer the value of n₃ to unity, the higher the voltage gain will be. However, larger turn ratios of the CI result in larger CI volume and make it difficult to control the converter. Hence, after selecting the desired voltage conversion ratio and the duty cycle, a compromise selection of n₂ and n₃ is more suitable combining (46) and (47).

Ignoring mode I, Diode D₄ turns off when switch S is turned on. The current of the output capacitor C_o is equal to the output current I_o. Ignoring the output current ripple and the ESR of the output capacitor result in:

()

Hence, by choosing the desirable output voltage ripple and switching frequency f_S, the value of output capacitor C_o could be calculated. According to Figure 2, the voltage and current stresses on the semiconductor devices could be obtained as follows:

()

The maximum current flowing through diode D₃ is given in (30). The peak current of switch S and diodes could be achieved as follows.

()

4. Comparison Study

In Table 1, the proposed converter is compared to some converters presented before in terms of the number of components, input current ripple, voltage gain, voltage stresses across semiconductors, and the type of switching.

Table 1. Comparison of the proposed converter with some step-up DC-DC converters.

Ref.	Number of components					Low ripple input current	S.S	Voltage gain	(Sum of) Voltage stress on switch (es)	∑V_D
Ref.	D	S	C	CI/I	T	Low ripple input current	S.S	Voltage gain	(Sum of) Voltage stress on switch (es)	∑V_D
P.C	4	1	5	1^3w/1	12	YES	YES	(n₂ + 2 + (n₂ + 1)D − n₃)/((1 − n₃)(1 − D))	(M(1 − n₃) + n₂ + 1)/(3 + 2n₂ − n₃)V_in	((4 + 3n₂ − n₃)[M(1 − n₃) + n₂ + 1])/((1 − n₃)(3 + 2n₂ − n₃))V_in
[16]	4	1	5	1^2w/1	12	YES	NO	(2 + D/n − 1)/(1 − (n/n − 1)D)	(M(n + 1))/(M + 2n)V_in	(M(n + 1)(3n − 1))/((n − 1)(M + 2))V_in
[17]	4	2	6	1^2w/2	15	YES	YES	(2 + D/n − 1)/(1 − (n/n − 1)D)	(2M(n + 1))/(M + 2n)V_in	(M(n + 1)(3n − 1))/((n − 1)(M + 2))V_in
[18]	2	1	3	1^2w/1	8	YES	NO	(1 + (nD/n − 1))/(1 − D)	((n − 1)M + n)/(2n − 1)V_in	(M + n/n − 1)V_in
[19]	5	1	6	1^3w/0	13	NO	NO	(2 + n(2 − D)/(1 − 2D))	(2M − n)/(4 + 3n)V_in	(2M − n)V_in
[20]	5	1	5	1^3w/0	12	NO	NO	(3 + 2n₂ + n₃)/(1 − D)	(M/3 + 2n₂ + n₃)V_in	((5 + 4n₂ + 2n₃)M)/(3 + 2n₂ + n₃)V_in
[21]	4	1	4	1^3w/0	10	NO	YES	((1 + n₂)(1 − D) + 2 + n₃)/(1 − D)	(M − n₂ − 1)/(2 + n₃)V_in	((M − n₂ − 1)(4 + n₂ + 2n₃))/(2 + n₃)V_in
[22]	5	1	6	1^3w/1	14	YES	YES	n₂ + n₃ + ((n₂ + n₃)D + 1)/(1 − D)	(M/1 + n₂ + n₃)V_in	(2M − M/1 + n₂ + n₃)V_in
[23]	5	1	3	1^3w/1	11	YES	NO	((n₂ + n₃)D)/(1 − D) + (1/(1 − D)²)	(V_in/(1 − D)²)	((1 + n₂ + n₃/(1 − D)) + (1 + D + D(n₂ + n₃)/(1 − D)²))V_in
[24]	3	1	4	1^3w/1	10	YES	YES	(2 + n₂ − n₃(1 − D))/((1 − n₃)(1 − D))	(M(1 − n₃) − n₃)/(2 + n₂ − 2n₃)V_in	(3 + 2n₂ − 4n₃D)/((1 − n₃)(1 − D))V_in
[25]	3	1	4	1^3w/1	10	YES	YES	(n₃ + n₂(1 + D) − D)/((n₂ − 1)(1 − D))	(M(n₂ − 1) + n₂ + n₃ − 1)/(2(n₂ + n₃) − 1)V_in	(2(n₂ + n₃)[M(n₂ − 1) + n₂ + n₃ − 1])/((n₂ − 1)[2(n₂ + n₃) − 1])V_in
[26]	2	2	4	1^3w/1	10	YES	YES	(2 + n₂ − n₃)/((1 − n₃)(1 − D))	2((1 − n₃)/(2 + n₂ − n₃))MV_in	2((1 + n₂)/(2 + n₂ − n₃))MV_in
[27]	4	1	5	1^3w/1	12	YES	NO	(2 + n₂)/((1 − n₃)(1 − D))	(M/2 + n₂)V_in	((3 + 2n₂ + n₃)/(2 + n₂))MV_in
[28]	4	1	5	1^3w/1	12	YES	YES	(2 + (2 − D)n₂ − (1 + D)n₃)/((1 − n₃)(1 − D))	(M(1 − n₃) − (n₂ + n₃))/(2 + n₂ − 2n₃)V_in	(5 + 3n₂ − (4 + D)n₃)/((1 − n₃)(1 − D))V_in

Abbreviations: C, capacitor; D, diode; L.I.C.R: low input current ripple; M.C, magnet core; S, switch; S.S, soft switching; T, total.

Figure 4 shows the voltage conversion ratios of the presented structure and references mentioned in Table 1 for n₂ = 2 and n₃ = 0.3. It is worth noting that converters presented in [16–18] are based on two-winding CI. Hence, their tertiary winding turns ratio is zero. As depicted in this figure, the duty cycle of the switch (D) is restricted in converters presented in [16, 17, 19]. According to this figure, the voltage gain of the proposed converter is higher than others for D > 0.5.

The normalized voltage stress on the switch (V_S/V_in) of the converters in Table 1 versus voltage gain is shown in Figure 5. As depicted in this figure, voltage stress across the switch of the proposed converter is less than all other converters except converter presented in [16]. However, this converter suffers from drawbacks including low voltage gain and hard switching performance.

In Figure 6, the normalized sum of voltage stresses on the diodes of the proposed converter and other converters are compared. Like Figure 5, the X axis is voltage gain. As illustrated in this figure, converters presented in [16–18, 25] have lower values than the proposed converter. This value is approximately equal for the proposed converter and the converter in [26]. The drawbacks of the converter in [18] are similar to the converter in [16]. Moreover, the converter in [25] has lower voltage gain and higher switch voltage stress in comparison with the proposed converter.

The other analytical procedure to evaluate the proposed converter and compare it with other structures is component stress factor analysis [29]. The motivation to use this method is that CSF considers voltage stresses and root mean square (RMS) current of components in a specific set of conditions and the power delivered to the output load and gives a quantitative measure of converter performance [30]. The other method which is similar to CSF is component load factor (CLF) analysis [31]. The difference between these two approaches is how the individual and total component factors are calculated. To perform CSF analysis, it is assumed that topologies under study have the same resources of silicon, magnetic winding area, and capacitor volume. Therefore, CSF analysis includes three different parts: Semiconductor component stress factor (SCSF), winding component stress factor (WCSF), and capacitor component stress factor (CCSF). These parameters could be formulated as follows [29].

()

Where SCSF_i, WCSF_i, and CCSF_i are the CSF of each semiconductor, inductor and capacitor, respectively. Coefficients W_j and ∑_jW_j represent the weight assigned to component i and the sum of weights assigned to a component of the same type, respectively. Symbol P is the power delivered by the converter. The total CSF of each component of the same type could be calculated as follows.

()

Where N_S, N_W, and N_C symbolize the number of semiconductors, inductors, and capacitors of the converter, respectively. To simplify the analysis, it is assumed that capacitors and inductors are large enough without any ripples in these voltages and currents, respectively. It is also assumed that there is no power dissipation in the structure. Hence, both input and output powers are equal (P_in = P_out).

The semiconductors CSF of the proposed converter and some of the converters mentioned in Table 1 at the output power of 200 W are depicted in Figure 7. The SCSF of each structure is calculated with the same weighting factor. For simplicity, the weighting coefficient ∑_jW_j is assumed to be unit and distributed equally between the semiconductors of each converter.

As illustrated in this figure, the converter in [20] has the lowest SCSF. However, for duty ratios more than 0.5, its voltage gain is lower than the proposed converter. Moreover, this converter has other drawbacks such as discontinuity of the input current and hard switching performance of the semiconductors which make it unpromising for PV applications and decrease its efficiency. The converter in [27] has lower SCSF than the proposed converter for voltage gains lower than 20. By increasing voltage conversion ratio to values more than 20, it will have more SCSF in comparison with the proposed converter. Like the converter in [20], the hard switching performance of the semiconductors of the converter in [27] is the other drawback of this converter.

The effect of turn ratios n₂ and n₃ on SCSF is shown in Figure 8. According to this figure, as turn ratios increase, SCSF value increases for lower voltage gains. However, for higher voltage gains, the SCSF value is reduced by increasing turn ratios.

5. Efficiency Analysis

The power losses of the components of the converter are related to the switch, diodes, capacitors, and magnetic device losses. The equivalent circuit of the proposed converter considering parasitic parameters is depicted in Figure 9. Assuming that currents flowing through inductors are ripple-free, the RMS values of inductor currents will be equal to their average currents. It is worth noting that modes I and III are neglected in efficiency analysis. The switch losses include switching and conduction losses and could be achieved as:

()

Regarding that the switch turns on under ZCS conditions, P_SW(off) and P_C,S are the turn-off switching and conduction losses of the switch, respectively. Their values could be obtained as:

()

Where V_S is the voltage stress across the switch S, I_on is the switch current prior to the turn-off of the switch, t_off is the transition time until the switch is turned off, I_S,rms is the RMS value of the current flowing through switch S. Utilizing the current flowing through the switch, the RMS value of the switch current could be obtained.

()

Where T_S is the switching period. The RMS value of the current flowing through the switch could be given by:

()

Selecting IRFP260 as the switch along with substituting (49) and (63) into (60) and (61), power losses of the switch could be obtained. All diodes turn off at ZSC condition. Hence, diode losses could be given by:

()

Where I_D,rms, and I_D,avg are the RMS and average values of each diode current, and r_D and V_F represent the conduction resistance and voltage drop of each diode, respectively. The currents flowing through diodes could be given by:

()

It could be proved that the average currents of all diodes are equal to the output current I_O. Utilizing (65)–(67), the RMS values of diode currents could be obtained as follows:

()

Selecting MUR1560 for all diodes along with substituting (68)–(70) into (64), power losses of diodes could be calculated as follows.

()

The losses of the capacitors and the inductor are caused by their ESR (r_C) and DC resistance, respectively. Their power losses could be given by:

()

Where I_C,rms, and I_Lk,rms represent the RMS values of capacitor and CI current, respectively. Meanwhile, r_Lin and r_L1 are DC resistances of the input inductor and the CI, respectively. The RMS values of capacitors’ and inductors’ currents could be given as follows:

()

By substituting (74)–(77) into (72), power losses of capacitors could be calculated. The RMS values of currents flowing through the inductor and CI could be achieved as below.

()

The contribution of components of the presented converter in total power losses is shown in Figure 10. Total power losses of the converter could be obtained by the sum of individual power dissipations in each component. It yields to:

()

The efficiency of the proposed converter could be formulated as follows.

()

Where P_O is the output power of the converter. Utilizing (59), (71), (72) along with (73) and substituting (80) into (81), the efficiency of the proposed DC-DC converter can be formulated as follows:

()

Where R_L is the output load and A₁ and A₂ are given by the following.

()

It can be demonstrated that the actual voltage gain of the proposed converter can be obtained by multiplying the ideal voltage gain (considering the leakage inductance of the CI) by the converter’s efficiency. Therefore, we can express it as:

()

Hence, the real voltage gain of the presented structure could be given as follows.

()

In Figure 11, the calculated efficiency of the converter as a function of duty ratio for different output power is depicted. According to this figure, the efficiency of the converter is more than 94% for duty ratios of more than 0.5 and output power up to 250 W. As the duty ratio increases, efficiency of the converter gets higher as well. This trend continues for duty ratios less than 0.85.

In Figure 12, the impact of turns ratios on the efficiency of the structure is depicted. As illustrated in this figure, as turns ratios n₂ and n₃ increase, the efficiency of the proposed topology reduces.

The theoretical and measured efficiencies of the presented structure and the converter in [27] versus output power are depicted in Figure 13. According to this figure, the measured efficiency of the structure reaches the peak of 95.2% at the output power of 75 W. In contrast, the measured efficiency of the converter in [27] reaches its peak of 94.2% at the output power of 180 W. As the output power increases, the efficiencies of both converters decrease slowly. As is shown in the figure, at the output power of 200 W, the theoretical efficiency of the presented converter is about 95.5%. However, the measured efficiencies of the proposed converter and converter in [27] are about 94%.

6. Experimental Results

To validate the function and theoretical analysis of the presented converter, a 200 W prototype converter operating at the frequency of 50 kHz is constructed. Figure 14 shows the experimental prototype of the proposed converter. Different components are named in this figure as well. Table 2 lists the specifications of the proposed structure. Finally, the voltage and current waveforms of the components are given in Figure 15. The presented converter boosts the input voltage of 25 V to the output voltage of 400 V at the output power of 200 W. Hence, the real voltage conversion ratio, the output current, and the load value could be calculated as follows:

()

Table 2. The circuit parameters of the implemented prototype.

Parameter	Value
Input voltage (V_in)	25 V
Output voltage (V_O)	400 V
Output power (P_O)	200 W
Capacitors (C₁ − C₄)	47 µF
Output capacitor (C_O)	180 µF
Input inductor (L_in)	320 µH
Magnetizing inductance of CI (L_m)	100 µH
Turns ratio of CI (n₂ & n₃)	n₂ = 2 & n₃ = 0.2
Switching frequency (f_S)	50 kHz
Power switch (S)	IRFP260
Diodes (D₁ − D₄)	MUR1560

Selecting n₂ = 2 and n₃ = 0.2, and according to (29), the ideal duty ratio could be calculated as follows:

()

According to Figure 11, the converter’s calculated efficiency is about 95.5% at the output power of 200 W and duty cycle of 0.57. Neglecting the effect of the leakage inductance of the CI, the ideal voltage gain of the presented structure could be given by:

()

Utilizing (90), the actual value of the duty cycle D can be expressed as follows:

()

6.1. Semiconductors

According to (30), and (49) to (52), the voltage and the current stresses of the switch and diodes could be calculated as follows.

()

Therefore, the appropriate switch and diodes can be selected based on these values.

6.2. Capacitors

To have a voltage with the lowest possible ripple, the voltage ripple of 0.05% of the voltage on the capacitor is selected. Therefore, the minimum suitable value for capacitors is calculated as follows.

()

Hence, values of capacitors C₁ to C₄ are selected to be 47 μF and the output capacitor value is selected to be 180 μF to guarantee the lowest ripple for output voltage.

6.3. Inductors

Utilizing (42), the minimum value of the input inductor could be given by:

()

To reduce the input ripple current, the value of the input inductor L_in is selected to be 320 µH. The minimum value of magnetizing inductance of the CI could be achieved as follows.

()

Figure 15(a) represents currents flowing through the input inductor, the CI, the switch S, and the diode D₁. As depicted in this figure, the input current ripple is relatively low. Hence, the presented converter is a functional solution for PV systems. According to this figure, the switch S turns on and the diode D₁ turns off under ZCS condition. Voltages across switch S and diode D₁ along with the currents flowing through diodes D₃ and D₄ are given in Figure 15(b). Meanwhile, Figure 15(c) shows the voltages across the diodes D₃ and D₄ along with the voltage of the capacitor C₁. Finally, Figure 15(d) illustrates the voltages of capacitors C₂, C₃, C₄ and the output voltage. According to this figure, all diodes are turned off in ZCS mode. Hence, the power dissipation is low and the efficiency of the converter is relatively high. Meanwhile, the reverse recovery problems of all diodes are alleviated. Figure 15(e) shows the dynamic performance of the converter to a step change of output voltage. As depicted in this figure, the output voltage is decreased by about 30 V and raised again to 400 V. As it is seen, it takes a short time (about 300 ms) for the converter to follow the output change.

7. Conclusion

In this paper, a non-isolated trans-inverse high gain SEPIC-based DC-DC converter has been studied thoroughly for PV applications. To achieve high conversion ratio, a three-winding CI along with an improved VM cell has been utilized. However, unlike other CI-based DC-DC structures, the voltage gain could be increased by raising and lowering the secondary and tertiary winding turns ratio, respectively. Moreover, a passive voltage clamp has been employed to reduce voltage stress on the switch and recycle the energy stored in the leakage inductance of the CI. Hence, a switch with low R_DS−ON has been used. Not only ZCS characteristics of semiconductors reduce switching losses and increases the efficiency of the converter, but also alleviate the reverse recovery problem of all diodes. Steady-state analysis of the structure has been discussed. Component design considerations are formulated and requirements for selecting semiconductors, inductors, and output capacitor has been taken into account. Furthermore, the presented converter and some other CI-based converters have been compared in terms of voltage gain, number of components, type of switching, voltage stresses on semiconductors, and continuity of the input current. The comparison results determined the advantages of the proposed topology over other converters. At the end, a 200-W laboratory prototype has been implemented and experimental results have been given in order to confirm the feasibility of the structure.

Conflicts of Interest

There is not any conflict of interest.

Funding

I declare on behalf of all authors that there is no funding for this article.

Open Research

Data Availability Statement

There is not data availability for this manuscript.

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Study on a Trans-Inverse High Gain SEPIC-Based DC-DC Converter With ZCS Characteristics for Photovoltaic Applications

Abstract

1. Introduction

2. Operating Principles and Steady State Analysis of the Proposed Converter

2.1. Mode I [t₀ − t₁]

2.2. Mode II [t₁ − t₂]

2.3. Mode III [t₂ − t₃]

2.4. Mode IV [t₃ − t₄]

2.5. Mode V [t₄ − t₅]

3. Design of the Proposed Converter

4. Comparison Study

5. Efficiency Analysis

6. Experimental Results

6.1. Semiconductors

6.2. Capacitors

6.3. Inductors

7. Conclusion

Conflicts of Interest

Funding

Open Research

Data Availability Statement

References

Figures

References

Information

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Study on a Trans-Inverse High Gain SEPIC-Based DC-DC Converter With ZCS Characteristics for Photovoltaic Applications

Abstract

1. Introduction

2. Operating Principles and Steady State Analysis of the Proposed Converter

2.1. Mode I [t0 − t1]

2.2. Mode II [t1 − t2]

2.3. Mode III [t2 − t3]

2.4. Mode IV [t3 − t4]

2.5. Mode V [t4 − t5]

3. Design of the Proposed Converter

4. Comparison Study

5. Efficiency Analysis

6. Experimental Results

6.1. Semiconductors

6.2. Capacitors

6.3. Inductors

7. Conclusion

Conflicts of Interest

Funding

Open Research

Data Availability Statement

References

Figures

References

Related

Information

2.1. Mode I [t₀ − t₁]

2.2. Mode II [t₁ − t₂]

2.3. Mode III [t₂ − t₃]

2.4. Mode IV [t₃ − t₄]

2.5. Mode V [t₄ − t₅]