Volume 67, Issue 6 e70269
RESEARCH ARTICLE

Impedance Mismatch Approach to Design RF Power Amplifier With Harmonic Suppression

Saurabh Shukla

Saurabh Shukla

Department of Electrical Engineering, Indian Institute of Technology Jodhpur, Jodhpur, Rajasthan, India

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Soumava Mukherjee

Soumava Mukherjee

Department of Electrical Engineering, Indian Institute of Technology Jodhpur, Jodhpur, Rajasthan, India

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Arani Ali Khan

Corresponding Author

Arani Ali Khan

Department of Electrical Engineering, Indian Institute of Technology Jodhpur, Jodhpur, Rajasthan, India

Correspondence: Arani Ali Khan ([email protected])

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First published: 06 June 2025

ABSTRACT

This letter presents the design of a PCB based RF power amplifier (PA) with improved harmonic suppression without the use of any external filter at the output. The proposed stepped impedance microstrip line input and output matching networks offer optimum impedance matching at the fundamental design frequency, whereas at harmonics, the impedances are of no match with the impedances required for higher harmonics power. The designed PA delivers 12.5 watt of CW power in Class-AB mode of operation at 2.45 GHz with measured power added efficiency (PAE) and drain efficiency (DE) of 62.7% and 63.5%, respectively. The first three harmonics of the PA are suppressed at least by 38.9 dBc as well. Measured Gain and input return loss of the amplifier are within 19 ± 0.6 dB and better than 12 dB, respectively, over 2.38–2.65 GHz.

Data Availability Statement

Data sharing is not applicable to this article as no new data were created or analyzed in this study.

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