The implementation of a multi carrier-code division multiple access (MC-CDMA) base station receiver incorporating decision statistic ordered successive interference cancellation multi-user detection in low power CMOS hardware is investigated. Serial and parallel cancellation architectures are compared and it is shown that the parallel one operates in far fewer clock cycles than its serial counterpart. A detailed description of architecture is given including the parallel algoridim used to implement the multi-user detection. Results show the power consumption and fixed point performance of the circuit.

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Volume13, Issue5

September–October 2002

Pages 513-518

Implementation of a sic based MC-CDMA base station receiver^†

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Implementation of a sic based MC-CDMA base station receiver†

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Implementation of a sic based MC-CDMA base station receiver^†