Abstract
The sections in this article are
- 1 Burn-In of Semiconductors
- 2 Modeling Yield
- 3 Cost Factors
- 4 Fault Coverage and Occurrence
- 5 Yield–Reliability Relation Models
- 6 Conclusions
- 7 Acknowledgments
Bibliography
- 1 A. G. Sabnis VLSI Electronics Microstructure Science, Vol. 22, VLSI Reliability, San Diego, CA: Academic Press, 1990.
- 2 E. R. Hnatek Integrated Circuit Quality and Reliability, 2 ed., New York: Marcel Dekker, 1995.
- 3 World Semiconductor Trade Statistics (WSTS), Press Release, May 2001, Spring Forecast Session, May 15–18, 2001 [Online]. Available WWW: http://www.wsts.org
- 4 W. Kuo W. T. K. Chien T. Kim Reliability, Yield, and Stress Burn-in, Norwell, MA: Kluwer Academic, 1998.
- 5 A. Amerasekera D. S. Campbell Failure Mechanisms in Semiconductor Devices, New York: Wiley, 1987.
- 6 M. Campbell Monitored burn-in improves VLSI IC reliability, Computer Design, 24 (4): 143–146, April 1985.
- 7 D. L. Denton D. M. Blythe The impact of burn-in on IC reliability, J. Environ. Sci., 29 (1): 19–23, Jan./Feb. 1986.
- 8 W. Kuo Y. Kuo Facing the headaches of early failures: A state-of-the-art review of burn-in decisions, Proc. IEEE, 71: 1257–1266, 1983.
- 9 D. Chi W. Kuo Burn-in optimization under reliability & capacity restrictions, IEEE Trans. Reliab., 38: 193–198, 1989.
- 10 K. Chou K. Tang “Burn-in time and estimation of change-point with Weibull–exponential mixture distribution,” Decision Sci., 23 (4): 973–990, 1992.
- 11 D. G. Nguyen D. N. P. Murthy Optimal burn-in time to minimize cost for products sold under warranty, IIE Trans., 14 (3): 167–174, 1982.
- 12 W. Kuo et al. Optimal Reliability Design: Fundamentals and Applications, Cambridge UK: Cambridge University Press, 2000.
- 13 MIL-STD-280A, Definitions of Item Levels, Item Exchangibility, Models and Related Terms, Philadelphia: The Naval Publications and Forms Center, 1969.
- 14 W. T. K. Chien W. Kuo A nonparametric approach to estimate system burn-in time, IEEE Trans. Semicond. Manuf., 9: 461–466, 1996.
- 15 C. W. Whitbeck L. M. Leemis Component vs system burn-in techniques for electronic equipment, IEEE Trans. Reliab., 38: 206–209, 1989.
- 16 W. Kuo Reliability enhancement through optimal burn-in, IEEE Trans. Reliab., R-33: 145–156, 1984.
- 17 W. T. K. Chien W. Kuo Modeling and maximizing burn-in effectiveness, IEEE Trans. Reliab., 44: 19–25, 1995.
- 18 L. M. Leemis M. Beneke Burn-in models and methods: A review, IIE Trans., 22 (2): 172–180, 1990.
- 19 W. Kuo Incompatibility in evaluating large-scale systems reliability, IEEE Trans. Reliab., 43: 659–660, 1994.
- 20 M. Haim Z. Porat Bayes reliability modeling of a multistate consecutive K-out-of-n: f system, Annual Reliability and Maintainability Symp., 1991, pp. 582–586.
- 21 W. T. K. Chien W. Kuo A nonparametric Bayes approach to decide system burn-in time, Naval Res. Logist., 44 (7): 655–671, 1997.
- 22 T. A. Mazzuchi N. D. Singpurwalla A Bayesian approach for inference for monotone failure rates, Statist. Probab. Lett., 37: 135–141, 1985.
- 23 E. Takeda et al. VLSI reliability challenges: From device physics to wafer scale systems, Proc. IEEE, 81: 653–674, 1993.
- 24 D. L. Crook Evolution of VLSI reliability engineering, Proc. International Reliability Physics Symp., 1990, pp. 2–11.
- 25 A. Christou Integrating Reliability into Microelectronics Manufacturing, Chichester: Wiley, 1994.
- 26 C. Hu Future CMOS scaling and reliability, Proc. IEEE, 81: 682–689, 1993.
- 27 J. A. Shideler et al. A systematic approach to wafer level reliability, Solid State Technol., 38 (3): 47, 48, 50, 52, 54, March 1995.
- 28 T. A. Dellin et al. Wafer level reliability, SPIE Microelectronics Manufacturing and Reliability, Proc. Int. Soc. Opt. Eng., 1992, pp. 144–154.
- 29 A. P. Bieringer et al. Implementation of a WLR-program into a production line, 1995 IRW Final Report, 1996, pp. 49–54.
- 30 S. Garrard Production implementation of a practical WLR program, 1994 IRW Final Report, 1995, pp. 20–29.
- 31 T. E. Kopely et al. Wafer level hot-carrier measurements for building-in reliability during process development, 1994 IRW Final Report, IEEE Int. Integrated Reliability Workshop, 1995, pp. 57–59.
- 32 L. N. Lie A. K. Kapoor Wafer level reliability procedures to monitor gate oxide quality using V ramp and J ramp test methodology, 1995 IRW Final Report, IEEE Int. Integrated Reliability Workshop, 1996, pp. 113–121.
- 33 O. D. Trapp (ed.) 1991 International Wafer Level Reliability Workshop, Lake Tahoe, CA, 1991.
- 34 T. E. Turner Wafer level reliability: Process control for reliability, Microelectron. Reliab., 36 (11/12): 1839–1846, 1996.
- 35 J. M. Soden R. E. Anderson IC failure analysis: Techniques and tools for quality and reliability improvement, Proc. IEEE, 81: 703–715, 1993.
- 36 B. Schlund et al. A new physics-based model for time-dependent dielectric breakdown, Proc. Int. Reliability Physics Symp., 1996, pp. 84–92.
- 37 T. Kim W. Kuo Optimal burn-in decision making, J. Quality Reliab. Int., 14 (6): 417–423, 1998.
- 38 E. R. Hnatek A realistic view of VLSI burn-in II, Evaluation Eng., 28 (2): 80, 82–86, 89, 1989.
- 39 H. E. Hamilton An overview—VLSI burn-in considerations, Evaluation Eng., 31 (2): 16, 18–20, 1992.
- 40 D. Romanchik Why burn-in ICs ? Test & Measurement World, 12 (10): 85–86, 88, Oct. 1992. D. F. Frost K. F. Poole A method for predicting VLSI-device reliability using series models for failure mechanisms, IEEE Trans. Reliab., R-36: 234–242, 1987.
- 41 D. Romanchik Burn-in: Still a hot topic, Test & Measurement World, 12 (1): 51–52, 54, Jan. 1992.
- 42 D. Gralian Next generation burn-in development, IEEE Trans. Compon. Packag. Manuf. Technol. B, Adv. Packag., 17: 190–196, 1994.
- 43 B. Vasquez S. Lindsey The promise of known-good-die technologies, MCM ′94 Proc., 1994, pp. 1–6.
- 44 A. Martin et al. Assessing MOS gate oxide reliability on wafer level with ramped/constant voltage and current stress, 1995 IRW Final Report, IEEE Int. Integrated Reliability Workshop, 1996, pp. 81–91.
- 45 A. D. Singh On wafer burn-in strategies for MCM die, Int. Conf. Exhibition Multichip Modules, 1994, pp. 255–260.
- 46 D. B. Tuckerman et al. A cost-effective wafer-level burn-in technology, Int. Conf. Exhibition on Multichip Modules, 1994, pp. 34–40.
- 47 W. G. Flynn L. Gilg A pragmatic look at wafer-level burn-in: The wafer-level known-good-die consortium, IECEM '96 Proc., 1996, pp. 287–292.
- 48 A. V. Ferris-Prabhu Introduction to Semiconductor Device Yield Modeling, Boston: Artech House, 1992.
- 49 C. H. Stapper R. J. Rosner Integrated circuit yield management and yield analysis: Development and implementation, IEEE Trans. Semicond. Manuf., 8: 95–102, 1995.
- 50 J. L. Stevenson J. A. Nachlas Microelectronics reliability predictions derived from components defect densities, Annual Reliability and Maintainability Symp., 1990, pp. 366–371.
- 51 F. Jensen Yield, quality and reliability—a natural correlation? in R. H. Matthews (ed.), Reliability ′91, London: Elservier Applied Science, 1991, pp. 739–750.
- 52 E. M. J. G. Bruls Reliability aspects of defect analysis, IEEE/ETC, 1993, pp.17–26.
- 53 J. G. Prendergast Reliability and quality correlation for a particular failure mechanism, Proc. Int. Reliability Physics Symp., 1993, pp. 87–93.
- 54 J. Van der Pol F. Kuper E. Ooms Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit fit and ppm reliability era, Microelectron. Reliab., 36 (11/12): 1603–1610, 1996.
- 55 B. El-Kareh A. Ghatalia A. V. S. Satya Yield management in microelectronic manufacturing, Proc. 45th Electronic Components Conf., 1995, pp. 58–63.
- 56 Integrated Circuit Engineering Corp., Cost Effective IC Manufacturing 1995, Scottsdale, AZ, 1995.
- 57 S. P. Cunningham C. J. Spanos K. Voros Semiconductor yield improvement: Results, and best practices, IEEE Trans. Semicond. Manuf., 8: 103–109, 1995.
- 58 C. H. Stapper F. M. Armstrong K. Saji Integrated circuit yield statistics, Proc. IEEE, 71: 453–470, 1983.
- 59 T. L. Michalka R. C. Varshney J. D. Meindl A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy, IEEE Trans. Semicond. Manuf., 3: 116–127, 1990.
- 60 C. H. Stapper The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions, IBM J. Res. Devel., 29: 87–97, 1985.
- 61 A. V. Ferris-Prabhu “Defect size variations and their effect on the critical area of VLSI devices,” IEEE J. Solid State Circuits, SC-20: 878–880, 1985.
- 62 C. H. Stapper Modeling of integrated circuit defects sensitivities, IBM J. Res. Devel., 27: 549–557 (1983).
- 63 C. H. Stapper Modeling of defects in integrated circuit photolithographic patterns, IBM J. Res. Devel., 28: 461–475, 1984.
- 64 W. Maly Modeling of lithography related yield loss for CAD of ULSI circuits, IEEE Trans. Comput.-Aided Design, CAD-4: 166–177, 1985.
- 65 C. Kooperberg Circuit layout and yield, IEEE J. Solid-State Circuits, 23: 887–892, 1988.
- 66 Z. Stamenkovic N. Stojadinovic New defect size distribution function for estimation of chip critical area in integrated circuit yield models, Electron. Lett. 28 (6): 528–530, 1992.
- 67 A. Ghatalia B. El-Kareh Yield Management in Microelectronic Manufacturing, Short Course Notes, Austin, TX: National Alliance for Photonics Education in Manufacturing, 1996.
- 68 T. J. Wallmark Design considerations for integrated electron devices, Proc. IRE, 48: 293–300, 1960.
- 69 A. V. Ferris-Prabhu Models for defects and yield, in I. Koren (ed.), Defect and Fault Tolerance in VLSI Systems, New York: Plenum Press, 1989, pp. 33–46.
- 70 C. H. Stapper Defect density distribution for LSI yield calculations, IEEE Trans. Electron Devices, ED-20: 655–657, 1973.
- 71 C. H. Stapper Fact and fiction in yield modeling, Microelectron. J., 20 (1/2): 129–151, 1989.
- 72 C. H. Stapper On yield, fault distributions and clustering of particles, IBM J. Res. Devel., 30: 326–338, 1986.
- 73 C. H. Stapper Large-area fault clusters and fault tolerance in VLSI circuits: A review, IBM J. Res. Devel., 33, 162–173, 1989.
- 74 B. T. Murphy Cost-size optima of monolithic integrated circuit, Proc. IEEE, 52: 1537–1545, 1964.
- 75 J. E. Price A new look at yield of integrated circuits, Proc. IEEE, 58: 1290–1291, 1970.
- 76 T. Okabe M. Nagata S. Shimada Analysis on yield of integrated circuits and a new expression for the yield, Electrical Eng. Japan, 92 (6): 135–141, 1972.
- 77 C. N. Berglund “A unified yield model incorporating both defect and parametric effects,” IEEE Trans. Semicond. Manuf., 9: 447–454, 1996.
- 78 D. Dance R. Jarvis Using yield models to accelerate learning curve progress, IEEE Trans. Semicond. Manuf., 5: 41–45, 1992.
- 79 Semiconductor Industry Association, 1978–1993 Industry Data Book, 1994.
- 80 Integrated Circuit Engineering Corp., Cost Effective IC Manufacturing 1998–1999, Scottsdale, AZ, 1997.
- 81 F. Corsi S. Martino Defect level as a function of fault coverage and yield, Proc. European Test Conf., 1993, pp. 507–508.
- 82 W. Willing A. Helland Establishing ASIC fault-coverage guidelines for high-reliability systems, Annual Reliability and Maintainability Symp., 1998, pp. 378–382.
- 83 H. H. Huston C. P. Clarke Reliability defect detection and screening during processing—theory and implementation, Proc. International Reliability Physics Symp., 1992, pp. 268–275.
- 84 T. W. Williams N. C. Brown Defect level as a function of fault coverage, IEEE Trans. Comput., C-30: 508–509, 1981.
- 85 S. C. Seth V. D. Agrawal On the probability of fault occurrence, in I. Koren (ed.), Defect and Fault Tolerance in VLSI Systems, New York: Plenum, 1989, pp. 47–52.
- 86 P. Maxwell R. Aitken Test sets and reject rates: All fault coverages are not created equal, IEEE Design and Test of Computers, 10 (1): 42–51, March 1993.
- 87 W. H. Schroen Process testing for reliability control, Proc. Int. Reliability Physics Symp., 1978, pp. 81–87.
- 88 F. Kuper et al. Relation between yield and reliability of integrated circuits: Experimental results and application to continuous early failure rate reduction programs, Proc. Int. Reliability Physics Symp., 1996, pp. 17–21.
- 89 T. Kim W. Kuo W. T. K. Chien A relation model of yield and reliability for gate oxide failures, 1998 Annual Reliability and Maintainability Symp., Anaheim, CA, 1998, pp. 428–433.
- 90 T. Kim W. Kuo Modeling manufacturing yield and reliability, IEEE Trans. Semicond. Manuf., 12: 485–492, 1999.
- 91 T. Kim W. Kuo W. T. K. Chien “Burn-in effect on yield,” IEEE Trans. Electron. Packag. Manuf., 23: 293–299, 2000.
- 92 T. Chen M. J. Wang “Fuzzy set approach for yield learning modeling in wafer manufacturing,” IEEE Trans. Semicond. Manuf., 12: 252–258, 1999.
- 93 M. Recio Strategy and tools for yield enhancement, Proc. SPIE Proc. Int. Soc. Opt. Eng., 3743: 122–129, 1999.
- 94 C. Jun et al. Simulation-based semiconductor chip yield model incorporating a new defect cluster index, Microelectron Reliab., 39 (4): 451–456, 1999.
- 95 C. J. McDonald New tools for yield improvement in integrated circuit manufacturing: Can they be applied to reliability? Microelectron. Reliab., 39 (6): 731–739, 1999.
- 96 P. W. Mason et al. Relationship between yield and reliability impact of plasma damage to gate oxide, Int. Symp. on Plasma Processinduced Damage, P2ID, 2000, pp. 2–5.
- 97 W. C. Riordan R. Miller J. Hicks Reliability versus yield and die location in advanced VLSI, Microelectron. Reliab., 39 (6): 741–749, 1999.
- 98 S. Tang New burn-in methodology based on IC attributes, family IC burn-in data, and failure mechanism analysis, Proc. Annual Reliability and Maintainability Symp., 1996, pp. 189–190.
- 99 W. Kuo T. Kim An overview of manufacturing yield and reliability modeling for semiconductor products, Proc. IEEE, 87: 1329–1344, 1999.
Reading List
- D. L. Erhart et al. On the road to building-in reliability, 1995 IRW Final Report, IEEE Int. Integrated Reliability Workshop, 1996, pp. 5–10.
- M. Pecht A. Dasgupta Physics-of-failure: an approach to reliable product development, 1995 IRW Final Report, 1996, pp. 1–4.
- C. H. Stapper W. A. Klaasen The evaluation of 16-Mbit memory chips with built-in reliability, Proc. Int. Reliability Physics Symp., 1992, pp. 3–7.
Wiley Encyclopedia of Electrical and Electronics Engineering
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