Diagnosis of Semiconductor Processes
First published: 27 December 1999
Abstract
The sections in this article are
- 1 General Methods For Yield Improvement in Semiconductor Manufacturing
- 2 Monitoring and Diagnosis at The Unit Process and Equipment Level
- 3 Monitoring/DIagnosis at the Process Flow Level
Bibliography
- 1 R. McIvor et al. Profiting from process improvement in the new semiconductor manufacturing environment, Technol. and Oper. Rev., December 1997.
- 2 J. Kabarian Statistical diagnosis of IC process faults, Ph.D. Dissertation, Electrical Engineering and Computer Science, Carnegie Mellon University, 1990.
- 3 S. P. Cunningham C. J. Spanos K. Voros Semiconductor yield improvement: Results and best practices, IEEE Trans. Semicond. Manuf., 8: 103–109, 1995.
- 4 H. T. Heineken J. Khare W. Maly Yield loss forecasting in the early phases of the VLSI design process, presented at IEEE 1996 Custom Integrated Circuits Conference.
- 5 A. Jee F. J. Ferguson Carafe: An inductive fault analysis tool for CMOS VLSI circuits, presented at 11th Annu. 1993 IEEE Test Symp.
- 6 W. Maly Cost of silicon viewed from design perspective, in Proc. 31st ACM/IEEE Design Autom. Conf. June 1994, pp. 135–142.
- 7 B. E. Stine D. S. Boning J. E. Chung Analysis and decomposition of spatial variation in integrated circuit processes and devices, IEEE Trans. Semicond. Manuf., 10: 24–41, 1997.
- 8 PDF Solutions Inc., PDFAB diagnosis module, Application Note, Winter 1994.
- 9 C. Yu et al. Use of short-loop electrical measurements for yield improvement, IEEE Trans. Semicond. Manuf., 8: 150–159, 1995.
- 10 N. Chang Monitoring, maintenance and diagnosis in a computer-integrated environment for semiconductor manufacturing, Ph.D. Dissertation. Electrical Engineering and Computer Sciences, University of California, Berkeley, 1990.
- 11 N. Chang C. Spanos Continuous equipment diagnosis using evidence integration: An LPCVD application, IEEE Trans. Semicond. Manuf., 4: 43–51, 1990.
- 12 K. K. Lin C. Spanos Statistical equipment modeling for VLSI manufacturing: An application for LPCVD, IEEE Trans. Semicond. Manuf., 3: 216–229, 1990.
- 13 G. S. May C. J. Spanos Automated malfunction diagnosis of semiconductor fabrication equipment: A plasma etch application, IEEE Trans. Semicond. Manuf., 6: 28–40, 1993.
- 14 F. Nadi A. Agogino D. Hodges Use of influence diagrams and neural networks in modeling semiconductor manufacturing processes, IEEE Trans. Semicond. Manuf., 4: 52–58, 1991.
- 15 B. Kim G. S. May An optimal neural network process model for plasma etching, IEEE Trans. Semicond. Manuf., 7: 12–21, 1994.
- 16 C. D. Himmel G. S. May Advantages of plasma etch modeling using neural networks over statistical techniques, IEEE Trans. Semicond. Manuf., 6: 103–111, 1993.
- 17 M. T. Mocella J. A. Bondur T. R. Turner Etch process characterization using neural network methodology: A case study, Proc. SPIE, 1994.
- 18 DYM Inc., private communication, July 1997.
- 19 M. W. Cresswell et al. A directed-graph classifier of semiconductor wafer-test patterns, IEEE Trans. Semicond. Manuf., 5: 255–263, 1992.
- 20 M. E. Zaghloul et al. A machine-learning classification approach for IC manufacturing control based on test-structure measurements, IEEE Trans. Semicond. Manuf., 2: 47–53, 1989.
- 21 T. Hosaka S. Arai H. Matsui Vehicle control system and method, U.S. Patent No. 4,809,175, February 1989.
- 22 L. A. Zadeh The role of fuzzy logic in the management of uncertainty in expert systems, Fuzzy Sets and Syst., 11: 1983.
- 23 R. Ramamurthi Self-learning fuzzy logic system for in situ, in-process diagnostics of mass flow controller (MFC), IEEE Trans. Semicond. Manuf., 7: 42–52, 1994.
- 24 D. C. Montgomery Introduction to Statistical Quality Control, New York: Wiley, 1985.
- 25 J. M. Lucas Combined Shewhart–CUSUM quality control schemes, J. Quality Technol. 14 (2), 1982.
- 26 C. Spanos Statistical process control in semiconductor manufacturing, Proc. IEEE, 80: 819–830, 1992.
- 27 C. J. Spanos et al. Real-time statistical process control using tool data, IEEE Trans. Semicond. Manuf., 5: 308–318, 1992.
- 28 G. E. P. Box G. M. Jenkins Time Series Analysis: Forecasting and Control, 2nd ed., San Francisco: Holden-Day, 1976.
- 29 C. J. Spanos private communication.
- 30 J. Y.-C. Pan J. M. Tenenbaum PIES: An engineer’s do-it-yourself knowledge system for interpretation of parametric test data, AI Magazine, 7 (4): 62–69, 1986.
- 31 J. Patrick Dishaw J. Y.-C. Pan AESOP: A simulation-based knowledge system for CMOS process diagnosis, IEEE Trans. Semicond. Manuf., 2: 94–103, 1989.
- 32 G. Box W. G. Hunter J. S. Hunter Statistics for Experimenters, New York: Wiley, 1978.
- 33 F. Hayers-Roth D. A. Waterman D. Lenat Building Expert Systems, Reading, MA: Addison-Wesley, 1983.
- 34 W. Zhang L. Milor A neural network based approach for surveillance and diagnosis of statistical parameters in IC manufacturing process, in IEEE/SEMI Int. Semicond. Manuf. Sci. Symp., 1993, pp. 115–125.
- 35 J. B. Khare W. Maly Yield-oriented computer-aided defect diagnosis, IEEE Trans. Semicond. Manuf., 8: 195–206, 1995.
Wiley Encyclopedia of Electrical and Electronics Engineering
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